1、1Chapter 7 Sequential Logic Design PrinciplesLatches and Flip-Flops Clocked Synchronous State-Machine Analysis Clocked Synchronous State-Machine DesignDigital Logic Design and Application2Question: perform a n-bit addition using only one 1-bit adder? C1S0X0 Y0C0X YCI COSC2S1X1 Y1C1反饋 C3S2X2 Y2C2利用反饋

2、和時鐘控制 X YCI COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn YnrippleadderC1C23X YCI COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn YnrippleadderC1C2暫存 X YCI COSCi+1SiXi YiCi時鐘控制 需要具有記憶功能的邏輯單元，能夠暫存運算結果利用反饋和時鐘控制 4Basic Conceptssequential logic circuitOutputs depends not only on the current inputs but also on the

3、 past sequence of inputs.Contain feedback loops or memory device.Feedback sequential circuit+ gatesclocked synchronous state machinelatch and flip-flopMemoryDevicesCombinationalCircuitsExternal InputOutputMemory circuits:Have stable states to store circuit states;Change its states with the external

4、inputs change.5Basic Concepts“State” embodies all the information about the past needed to predict current output based on current input. state variable, one or more bits of information.n bit 2n statesState information is stored in memory devicesMemoryDevicesCombinationalCircuitsExternal InputOutput

5、QnQn+16Clock signalsVery important with most sequential circuitsState variables change state at clock edgeclock tick1. Bi-stable deviceOscillator to Bi-stable circuits71Q1 oscillation（振蕩）Oscillation frequency depends on the propagation delay00101010Unstable（不穩定）QBi-stable（雙穩態） QNQQN=1 and Q=0QN=0 an

6、d Q=18Vin1Vout1Vin2Vout2Vout2Vin2= Vin2= Vout2穩態 stable 亞穩態 metastable QQ_LVin1 Vout1Vin2 Vout22. Analog Analysis達到穩態的條件：反相器得到穩定的反饋輸入Vin1= T2(T1(Vin1)Vin2= T1(T2(Vin2)9All sequential circuits are susceptible to metastable behavior.3. Metastable BehaviorThe noise will tend to drive a circuit at the m

7、etastable point toward one of the stable operating point.Apply a definite pulse width from a stable state to the other.StableStableMetastableQQ_L1000QQN12QQN113. Metastable BehaviorQN=0 Q=0QN=1 Q=1QN=1 and Q=0QN=0 and Q=1Bi-stable:Meta-stable:振蕩的最后結果受兩個反相器時延特性的影響，最終可能會穩定到一個雙穩態上，或者繼續振蕩。11Problems of

8、Bi-stable elementsCant decide the initial stateSusceptible to metastable behavior7.2 Latches and Flip-FlopsQQN12How to control it127.2 Latches and Flip-FlopsHow to control it?Screwdriver 螺絲起子Control inputs7.2.1 S-R latchQQNRS(1) S = R = 0 00The circuit retains last state. Q* = Q , QN* = QNQ = last Q

9、 , QN = last QN137.2.1 S-R Latches0 QQNRS12(2) S = 0, R = 1 1 R=1 Q=0 QN=1 R resets (clears) the Q to 0.100QQNRS0112(3) S = 1, R = 0 S=1 QN=0 Q=1 S sets (presets) the Q to 1.001 After the S or R input is negated,the latch remains in the state that it was forced into.147.2.1 S-R LatchesQQNRS(4) S = R

10、 = 1 00Q = QN = 0If both inputs are negated simultaneously11goes to an unpredictable next state, may in fact oscillate or enter the metastable stateforbiddenQQN001215S-R latch function descriptionQQNRSFunction TableLogic SymbolS QR QResetSet unstableConstraints: SR = 0S=R=1 is forbidden16S-R latch f

11、unction description0100 01 11 10QSRQ*000111ddQ* = S + RQCharacteristic Equation: 特性方程01S=1,R=0S=0,R=1S=XR=0S=0R=XFunction TableState transition diagram:狀態轉移圖17S-R latch operation0 00 11 01 1S RHold0 11 0 0 0 Q QNSRQQNMetastability is possibleif S and R are negatedsimultaneously.18S-R latch timing pa

12、rameterstpw(min)SRQtpLH(SQ)tpHL(RQ)MinimumPulse width輸入信號（S,R）至少必須保持tpw(min)使Q的狀態來得及改變。如果S=1的時間小于tpLH(SQ)，或R=1的時間小于tpHL(RQ)，則不能保證使Q的狀態發生改變。基本S-R 鎖存器 小結具有兩個穩定狀態輸入需滿足一定限制條件描述邏輯電路圖功能表（function table）狀態轉換真值表（State transition truth特征方程（ Characteristic Equation ）狀態轉移圖（State transition diagram）table)激勵表 (E

13、xcitation table)19由現態轉移至次態對輸入信號的要求20S-R鎖存器的動作特點被置位/復位后，即使信號被取消也可以暫存信號，直到下一個置位/復位信號的到來“鎖存”抗干擾能力低輸入信號能直接改變鎖存器的狀態（直接置位復位觸發器）對輸入有要求，使用不方便仍然受亞穩態影響當S=R=1，然后同時取消時S和R端輸入信號脈沖寬度過小217.2.2 S-R LatchesS_L = R_L = 1Q = last Q, QN = last QN S_L = 1, R_L = 0Q = 0, QN = 1 S_L = 0, R_L = 1Q = 1, QN = 0 S_L = R_L = 0Q

14、 = QN =1SRS QR QLogic SymbolFunction Table unstableQQNS_LR_LIf both inputs are negated simultaneously22S-R鎖存器的動作特點被置位/復位后，即使信號被取消也可以暫存信號，直到下一個置位/復位信號的到來“鎖存”抗干擾能力低輸入信號能直接改變鎖存器的狀態（直接置位復位觸發器）對輸入有要求，使用不方便仍然受亞穩態影響當置位/復位信號同時有效，然后同時取反時當置位/復位信號脈沖寬度過小237.2.3 S-R Latch with EnableSRCQQNS_LR_L0 X X1 0 01 0 11

15、1 01 1 1C S RlastQ lastQNlastQ lastQN0 11 0 1* 1* Q QNFunction Table(1). C=0:Q = last Q; QN = last QN(2). C=1:If S=R=1 when C changes from 1 to 0,the next state is unpredictable.SCRQQQuiz: c=1 時，使用Bubble to bubble分析方法，應等效為一個SR Latch，Why？A active high S-R latch24Timing Diagram0 X X1 0 01 0 11 1 01 1

16、1C S RlastQ lastQNlastQ lastQN 0 1 1 0 1* 1*Q QNQSRC動作特點：輸入信號在時鐘（使能端）有效期間，都能直接改變觸發器的狀態。257.2.4 D LatchesIf D=1, Q = 1C=0, QQNSRDCData inputControl inputENABLECLK、GQ holds its last valueD passes through to QC=1,If D=0, Q = 0Q = DtransparentC D Q QN1 0 0 11 1 1 00 x lastQ lastQNFunction TableD QC QLogic SymbolopaqueC Q* 1 D 0 last QFunction TableCharacteristic Equation: Q* = C D+ C Q 26D Latch function descriptionCharacteristic Equation: Q* = D (C=1) 01C=