1、1.概本手冊基于全志A20 debug能對DRAM2.1.概本手冊基于全志A20 debug能對DRAM2.DRAM調2.1A20in2.2 常用硬件調DRAM-VCC DRAM-VREF電壓是否正常，DRAM-VREFDRAM-VCC的一（DDR3 的DRAM-VCC 約為 1.5V 1.6V）測量主控端和DRAMZQ240ohm （1%精度s.-4 0.75V0.8V DDR顆粒BALLVDD 0.75V0.8V DDR顆粒BALLVDD VDD和VSS2.3 常調 = = = = = = = = = = = = = = = = = = = = MHz，24M dclk和地址線和DQ使用不

2、同的阻抗CA用dram_zq7:4DQ用dram_zqbit3:0計算公式為（240*2）N1)。240為SOCZQpinBit03為SOC端的DQ&CA ODT 阻抗。N 00 xF16擋可調，0 xB0 xFdram_emr10 x4（Rtt_NomRZQ/460ohm）s.-5 bit02T1T模式相關，bit1為配置DQCA bit02T1T模式相關，bit1為配置DQCA dBit1 。2.4 常見現象分析2.4.1 不彈出燒寫窗口 樣位置。或者可嘗試CKCK#0ohm100ohm2.4.2 固件燒寫失敗 勾頭調至遠離中心采樣位置。或者可嘗試 CK CK#0 ohm 電阻，跨接 10

3、0 ohm 電阻。 DRAM-VCC 電源層作為 CA 或者 DQ 的回流路徑不連續，比如s.-6 s.-7 dram_emr1 改為 0 x4。2.4.3 只識別一半DRAM 容 s.-8 版本更新說明版本更新說明s.-9 4.is the original work and copyrighted property of Allwinner (“Allwinner”). Reproduction in whole or in part must obtahewrittenapprovalofAllwinner and give clear acknowledgement to the co

4、pyright owner.The4.is the original work and copyrighted property of Allwinner (“Allwinner”). Reproduction in whole or in part must obtahewrittenapprovalofAllwinner and give clear acknowledgement to the copyright owner.The information furnished by Allwinner is beved to be accurate and reliable. Allwi

5、nner reserves the right to make changes in circuit design and/or specifications at any time notice. Allwinner does not me any responsibility and liability for its use. Nor for infringements of patents or other rights of the third parties ay result from its use. license is granted by implication or otherwise under any p