1、精選優質文檔-傾情為你奉上精選優質文檔-傾情為你奉上專心-專注-專業專心-專注-專業精選優質文檔-傾情為你奉上專心-專注-專業Assignment 91. Design an 8-bit up and down synchronous counter in VHDL with the following features:The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state).The counter is wit

2、h an asynchronous reset that assigns a specific initial value for counting.The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. Thi

3、s implies that when the load operation is in process the counter operation is prohibited.Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used.Synthesize the design. Create a set of reasonable input waveforms for your design and complete both behavioral and post-place&route s

4、imulations with internal signals and/or variables included in waveform or list windows. Solution:代碼如下：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this co

5、de.-library UNISIM;-use UNISIM.VComponents.all;entity count_8_bidir is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; load : in STD_LOGIC; enable : in STD_LOGIC; cnt : inout STD_LOGIC_VECTOR (7 downto 0); end count_8_bidir;architecture Behavioral of count_8_bidir issignal cnt_in: STD_LOGIC_VECTOR (7

6、 downto 0); signal cnt_out: STD_LOGIC_VECTOR (7 downto 0);begin pro0:process(oe,cnt_out,cnt) begin if(load=1)then cnt Z); cnt_in = cnt; else cnt = cnt_out; end if; end process; pro1:process(clk,rst) begin if(rst=1)then cnt_out 0); elsif rising_edge(clk)then if(load=1)then cnt_out = cnt_in; elsif(ena

7、ble=1)then cnt_out = cnt_out + 1; else cnt_out oe, clk = clk, rst = rst, load = load, enable = enable, cnt = cnt ); - Clock process definitions clk_process :process beginclk = 0;wait for clk_period/2;clk = 1;wait for clk_period/2; end process; - Stimulus process stim_proc: process begin rst=1; load=

8、0; enable=1; cntZ); wait for 100 ns; rst=0; wait for 500 ns; load=1; cnt=; wait for 200 ns; load=0; cntZ); wait for 500 ns; enable=0; wait for 500 ns;rst=1;wait; end process;END;根據TestBench的激勵可以看出：進入程序之后，首先復位且load=0，這時cnt_out從0開始做加法運算，當計數到5之后，load=1把cnt變成了輸入，并且給其賦了（轉化為整數為192），并且在上升沿條件下送到cin_out，此時ci

9、n_out=192；在加載該值之后，200ns之后將load=0將cnt變為輸出，此時cnt開始從192向上計數，記了經過500ns記到了197，然后遇到了enable=0，開始做減法，經過500ns，cnt變為192，隨后rst=1，將cnt清0，到此結束，功能驗證為正確。后仿真波形如上所示，與行為仿真的差別，就是前面幾百ps增加了一個Unknown狀態（沒有初始化的緣故），同時cnt相對于時鐘沿有延遲。2. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD an

10、d FPGA.Synthesize and verify (simulate) the VHDL design of the FIFOs;綜合后的RTL schematic和功能仿真后的結果分別如下圖1和圖2所示。圖1圖2For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells) and PTs (product terms) are needed? Which parameter is critical to the maximum internal clock working frequency? Try to

11、 find out this critical parameter and its corresponding circuit path.設置芯片為CoolRunner XPLA3 CPLDS系XCR3512XL-7-PQ208，速度為-7，綜合后報告分析如下 圖3為CPLD綜合報告：從報告中可以知道一共使用了87個MCs，占總體的17%，使用了208個PTs，占總體的14%，選這個型號似乎有點大材小用啊，不過資源很足夠，滿足設計的需求。圖4為CPLD時間報告：由圖 4可知，時鐘的最小周期為8.6ns，受clock to setup影響最大，故關鍵路徑為tcyc。延時為8.6ns，時鐘的工作頻

12、率為116.279MHz。圖3圖4For FPGA implementation (place and route) of the FIFOs, how many LBs (logic blocks)? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.設置芯片為更換芯片型號為Spartan3- xc3s200-5pq208,速度為-5，其綜合

13、報告如下圖5為FPGA綜合報告：圖5圖6為Spartan3 datasheet圖6圖7由上圖知，對于選擇的器件，其logic cell為4320,CLB 有24X20=480個，每個CLB包含4個slice,而對于我們的程序，一共使用了66個slice，占總數的百分之三（總slice共計1920個），故使用的CLB數為66/4=16.5，即使用了17個。由圖 7可知，時鐘的最小周期為5.078ns，受clock to setup影響最大，時鐘的工作頻率為196.927MHz。Try to synthesize again the design with timing constraints a

14、nd compare with its former counterparts. You will create the timing constraint file by yourself and add it to your project. Please refer to the following graphic interface of ISE:圖8為 timing constrain設置圖；圖9為沒有設置時序約束時的報告；圖10為設置CLK周期約束為5ns時的報告；圖11為設置CLK周期約束為4.5ns時的報告；圖 12 設置clk周期約束為4ns時的報告圖 13 設置clk周期約

15、束為3.5ns時的報告圖8圖9圖10圖11圖12圖13For the VHDL model given below (Code List Two), there may be some design errors in it. Some warning(s) and/or error(s) information may be issued when synthesizing it. Try to find out such design errors and correct them.仿真后無錯誤，有兩個警告如下圖：圖14(1) 程序中，輸入端口rd沒有使用到，其作用被oe所取代，因此可以將

16、rd信號去掉，用oe來表示其功能，且不影響整個系統的設計。(2) 程序中輸入信號端口en也未被使用，因為直接在fifo(wrptr)中取得了寫地址的值，因此信號en也應去掉。(3) 語句dmuxout=fifo(wrptr); 應改為dmuxout=fifo(rdptr); 因為這時是讀寄存器里的值，應該由讀地址指針rdptr來指定應該讀取哪個寄存器的值。改進后加入激勵得到圖15的輸出波形。圖158X9 FIFO BUFFER DESIGN EXAMPLES1# VHDL CODE LIST:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.S

17、TD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fifo89 is Port ( clk : in std_logic; rst : in std_logic; rd : in std_logic; wr : in std_logic; rdinc : in std_logic; wrinc : in std_logic; rdptrclr : in std_logic; wrptrclr : in std_logic; data_in : in std_logic_vector(8 downto 0); data_out :

18、 out std_logic_vector(8 downto 0);end fifo89;- clk: used to synchronize the buffers;- rst: reset the buffers- rd: when valid, the output buffers are enabled;- wr: when valid, write register with 9-bit width is permitted; - rdinc: read counter enabled;- wrinc: write counter enabled;- rdptrclr: reset

19、read counter, pointing to the first register for- read purpose;- wrptrclr: reset write counter, pointing to the first register for- write purpose;- data_in: data inputs with 9-bit width to the FIFOs;- data_out: data outputs with 9-bit width from the FIFOs.architecture Behavioral of fifo89 istype fif

20、o_array is array(7 downto 0) of std_logic_vector(8 downto 0);signal fifo: fifo_array;signal wrptr, rdptr: std_logic_vector(2 downto 0);signal en: std_logic_vector( 7 downto 0);signal dmuxout: std_logic_vector(8 downto 0);begin- fifo register_array:reg_array: process (rst, clk)beginif rst = 1 thenfor

21、 i in 7 downto 0 loopfifo(i) 0); - aggregateend loop;elsif (clkevent and clk = 1) thenif wr = 1 thenfor i in 7 downto 0 loopif en(i) = 1 thenfifo(i) = data_in;elsefifo(i) = fifo(i);end if;end loop;end if;end if;end process;- read pointerread_count: process (rst, clk)beginif rst = 1 thenrdptr 0);elsi

22、f (clkevent and clk = 1) thenif rdptrclr = 1 thenrdptr 0);elsif rdinc = 1 thenrdptr = rdptr + 1;end if;end if;end process;- write pointerwrite_count: process (rst, clk)beginif rst = 1 thenwrptr 0);elsif (clkevent and clk = 1) thenif wrptrclr = 1 thenwrptr 0);elsif wrinc = 1 thenwrptr = wrptr + 1;end

23、 if;end if;end process;- 8:1 output data muxwith rdptr selectdmuxout = fifo(0) when 000, fifo(1) when 001, fifo(2) when 010, fifo(3) when 011, fifo(4) when 100, fifo(5) when 101, fifo(6) when 110, fifo(7) when others;- FIFO register selector decoderwith wrptr selecten = when 000, when 001, when 010,

24、 when 011, when 100, when 101, when 110, when others;- three-state control of outputsthree_state: process (rd, dmuxout)beginif rd = 1 thendata_out = dmuxout;elsedata_out Z);end if;end process;end Behavioral;2# VHDL CODE LIST:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use I

25、EEE.STD_LOGIC_UNSIGNED.ALL;entity fifoxy is generic (wide: integer := 8); - width is 8 + 1 Port ( clk : in std_logic; rst : in std_logic; oe: in std_logic; rd : in std_logic; wr : in std_logic; rdinc : in std_logic; wrinc : in std_logic; rdptrclr : in std_logic; wrptrclr : in std_logic; data_in : in

26、 std_logic_vector(wide downto 0); data_out : out std_logic_vector(wide downto 0);end fifoxy;architecture Archfifoxy of fifoxy isconstant deep: integer := 7; - depth is 7 + 1type fifo_array is array(deep downto 0) of std_logic_vector(wide downto 0);signal fifo: fifo_array;signal wrptr, rdptr: integer range 0 to deep;signal en: std_logic_vector( deep