1、CPLD和FPGA的開發可編程邏輯器件PLD(Programmable Logic Device) 寧改娣目錄CPLD/FPGA概述CPLD/FPGA的結構CPLD/FPGA開發及軟件發展方向CPLD/FPGA概述PLD（ Programmable Logic Device）的發展歷程 早期的可編程邏輯器件PROM.UVEPROM.EEPROM 稍復雜的可編程器件PLA.PAL.GAL 復雜的PLDEPLD.CPLD.FPGA CPLD/FPGA概述CPLD/FPGA的特點 無需MASK費用，無制造風險 功能強大，可用于系統集成 所需資金投入少 節省時間，軟件易學CPLD/FPGA概述CPLD

2、/FPGA廠商概述ALTERA MAX系列，ClassicFLEX系列,ACEX系列，APEX系列,MercuryStratix,CYCLONEXILINX XC9500,CoolRunner,SPARTAN,VirtexLattice ispLSI,ispMACH系列.OCRA系列ispPACispGDS,ispGDXOthersACTEL,Cypress,quicklogic CPLD/FPGA的結構 乘積項原理 查找表原理 輸出等于abcd對應RAM內容CPLD/FPGA的結構CPLD的結構CPLD/FPGA的結構CPLD/FPGA的結構FPGA的結構xilinx Spartan-II

3、芯片內部結構 CPLD/FPGA的結構SpartanII實現邏輯的最基本結構 SlicesCPLD/FPGA的結構CPLD與FPGA的對比異： CPLD主要基于乘積項技術，EEPROM工藝 FPGA主要基于查找表技術，SRAM或FLASH工藝,一般外掛配置用的EEPROMFPGA包含的門數一般大于CPLD，即FPGA集成度較高同： 三大部分構成一個二維的邏輯塊陣列輸入輸出塊連接邏輯塊的互連資源實現功能相同CPLD/FPGA開發及軟件開發流程：設計準備原理圖硬件描述語言波形圖設計處理優化,綜合適配,分割布局,布線器件編程器件測試時序仿真功能仿真設計輸入CPLD/FPGA開發及軟件集成的CPLD/

4、FPGA開發環境Altera：MAXPLUSII QuartusIIXilinx：ISELattice：ispLEVERPAC DesignerCPLD/FPGA開發及軟件HDL邏輯綜合軟件 Synplify FPGAexpress Leonardo SpectrumCPLD/FPGA開發及軟件HDL仿真軟件 ModelSim VCS/Scirocco NC-Verilog/NC-VHDL/NC-SIMACTIVE-HDL CPLD/FPGA開發及軟件其他相關軟件 Debussy Visual IP X-HDL HDL前端輸入與系統管理軟件Visual VHDL/ Visual Verilog

5、CPLD/FPGA開發及軟件Xilinx的coolRunnerII設計工具價錢比較便宜，標準并行電纜，送ise軟件Altera新的Nios開發工具大容量的ram，以太網接口SOC實驗開發系統GW48SOC大容量的FPGA,高速的A/D,D/A含可編程模擬器件發展方向向SOPC（可編程芯片上系統）發展工藝越來越細功耗降低，產品易用性越來越好 4.IP庫的建設日益被重視 5.動態可重構技術的發展，將帶來系統設計方法的轉變FPGA補充FPGA ARCHITECTURE基于SRAMAnti_fusesFlashAn FPGA is essentially comprised of buffers, S

6、RAMs, multiplexers, LUTs, flip-flops,and pass-transistor switches.FPGA的布局圖（版圖）The FPGAs we consider are composed of three broad classes of structures logic blocks,programmable routing, and I/O pads.FPGA布局圖中布線和布線開關Figure 2.11.Routing Architectureisland-style（如圖所示）row-basedhierarchicalSwitches can be

7、simple pass transistors controlled by an SRAM cell, or can use a buffer to provide greater drive strength. Figure 2.2 shows both of these types of switches being used to connect different routing wires together.Ultimately, routing wires and routing switches are used to connect logic blocks together.

8、2.Logic Block Architecture可編程邏輯快基本單元通常由 multiplexers（MUX） 和 lookup-tables (LUTs)組成, 2種結構類似，都由傳輸晶體管（pass-transistors）網絡組成MUX和LUT結構不同之處是：SRAM被連接到MUX中晶體管的刪極gates；而在LUT中SRAM被連接到晶體管的源極source node。如圖2.Logic Block Architecture（續） MUX和LUT結構的不同Multiplexer schematic adapted from 1MUX采用的是NMOS傳輸電路Look-up Table

9、(LUT) schematic adapted from 12.Logic Block Architecture（續） Basic Logic Element (BLE)一個LUT與觸發器結合形成BLE，觸發器的出現就可以實現組合和時序電路2.Logic Block Architecture（續）An entire logic block can consist of one or more BLEs.實際邏輯電路LUT的實現方式a,b,c,d 輸入邏輯輸出地址RAM中存儲的內容00000000000001000010.0.011111111114輸入與門的例子 To allow logic

10、blocks to connect to routing wires, an FPGA has input connection blocks and output connection blocks. A set of typical input connection blocks is shown in Figure 2.4.ConclusionThe architecture of an FPGA is determined by many different parameters, each of which affects one or more of the building bl

11、ocks presented above. More detail about these parameters can be found in 1. For the purposes of our research, we used values for these parameters that were found to be good in 1.FPGA TilesAn FPGA of the form shown in Figure 2.1 is often implemented by designing only one logic block and the programma

12、ble routing around it, forming an FPGA “tile”.This single tile can, if designed properly, be duplicated and laid in a regular array to form the core of the FPGA. This process is shown in Figure 2.6, with a single tile being used to generate a 3-by-3 portion of the FPGA core.a single tileFPGA formed by repli