1、精選優質文檔-傾情為你奉上FPGA電路設計FIFO源代碼define ADDR_WIDTH 8 /地址位寬define DATA_WIDTH 8 /數據位寬define RAM_WIDTH 8 /RAM數據位寬define RAM_DEPTH 256 /RAM深度module fifo_test(clk_100M,/寫時鐘clk_5M, /讀時鐘rst_n,/ 全局復位信號wr_en,/ 寫使能 低有效rd_en,/ 讀使能 低有效wr_data,/8位數據輸入rd_data,/8位數據輸出wr_full,/ 寫滿標志 高有效rd_empty);/ 讀空標志 高有效/輸入信號 input cl

2、k_100M; input clk_5M; input rst_n; input wr_en; input rd_en; inputDATA_WIDTH-1:0 wr_data; output reg DATA_WIDTH-1:0 rd_data; output reg wr_full; output reg rd_empty; reg RAM_WIDTH-1:0 memRAM_DEPTH-1:0;/ 8位256單元regADDR_WIDTH-1:0 wr_addr; / 8位寫地址 regADDR_WIDTH-1:0 rd_addr; / 8讀地址reg rd_flag;reg wr_fla

3、g;/寫地址產生邏輯 always (posedge clk_100M or negedge rst_n) begin if(!rst_n)beginwr_addr <= 8'h0;wr_flag <= 0;end else if(!wr_en)beginif(!wr_full && (rd_addr!=(wr_addr+1)beginwr_flag <= 1;wr_addr <= wr_addr + 1'b1;endelsewr_flag <= 0;end end/ 寫數據產生邏輯 always (posedge clk_100M

4、) begin if(!wr_en && !wr_full && wr_flag) memwr_addr <= wr_data; end/寫滿產生標志 always (posedge clk_100M or negedge rst_n) begin if(!rst_n)wr_full <= 0; else if(rd_addr = (wr_addr+1)wr_full <= 1'b1;elsewr_full <= 1'b0; end/讀地址產生邏輯 always (posedge clk_5M or negedge rst

5、_n) begin if(!rst_n)beginrd_flag <= 0;rd_addr <= 8'd0;end else if(!rd_en)beginif(!rd_empty && (wr_addr!=(rd_addr+1)beginrd_flag <= 1;rd_addr <= rd_addr + 1'b1;endelserd_flag <= 0;end end/讀數據產生邏輯 always (posedge clk_5M) begin if(!rd_en && !rd_empty && rd

6、_flag) rd_data <= memrd_addr; end/讀空產生標志 always (posedge clk_5M or negedge rst_n) begin if(!rst_n)rd_empty <= 1'b1; else if(wr_addr = (rd_addr+1)|(wr_addr = rd_addr)rd_empty <= 1'b1;else rd_empty <= 1'b0; endendmodule/ 激勵源代碼：module fifo_test_IB; reg clk_100M;reg clk_5M; reg r

7、st_n; / 全局復位信號 reg wr_en; / 寫使能 reg rd_en; / 讀使能 regDATA_WIDTH-1:0 wr_data; wire7:0 rd_data;wire wr_full;wire rd_empty;reg7:0 cnt;fifo_test fifo1(clk_100M,clk_5M, rst_n,wr_en,rd_en,wr_data,rd_data,wr_full,rd_empty);always #15 clk_5M = clk_5M; /讀時鐘always #5 clk_100M = !clk_100M; /寫時鐘initialbegin rst_n = 0; clk_100M = 0; clk_5M = 1; wr_en = 0; rd_en = 0; #25 rst_n = 1; endalways (posedge clk_100M or negedge rst_n)beginif(!rst_n)wr_data <= 8'd0;else wr_data <= cnt;endalways