1、stm32中用到的cortex在中用到了-m3定義的三組寄存器，有關這三組寄存器的解釋不在stm32的技術手冊中，需要參考公司發布的cortex-m3 technical reference manual (r2p0)。在stm32的固件庫中定義了三個結構體與這三個寄存器組相對應，這三個結構體與arm手冊中寄存器的對應關系如下：一、nvic寄存器組stm32的固件庫中有如下定義：typedef structvu32 iser2;u32 reserved030;vu32 icer2;u32 rserved130;vu32 ispr2;u32 reserved230;vu32 icpr2;u32

2、reserved330;vu32 iabr2;u32 reserved462;vu32 ipr11; nvic_typedef;它們對應arm手冊中的名稱為iser = interrupt set-enable registersicer = interrupt clear-enable registersispr = interrupt set-pending registericpr = interrupt clear-pending registeriabr = active bit registeripr = interrupt priority registers每個寄存器有240位

3、，以interrupt set-enable registers解釋，iser0對應中斷源031，iser1對應中斷源3263，stm32惟獨60個中斷源，所以沒有iser2:7。參考stm32技術參考手冊中的中斷向量表，中斷源的位置為：位置0 - wwdg = window watchdog interrupt位置1 - pvd = pvd through exti line detection interrupt位置2 - tamper = tamper interrupt.位置58 - dma2_channel3 = dma2 channel3 global interrupt位置59

4、- dma2_channel4_5 = dma2 channel4 and dma2 channel5 global interrupts二、系統控制寄存器組stm32的固件庫中有如下定義：typedef structvuc32 cpuid;vu32 i;vu32 vtor;vu32 aircr;vu32 scr;vu32 ccr;vu32 shpr3;vu32 shcsr;vu32 cfsr;vu32 hfsr;vu32 dfsr;vu32 mmfar;vu32 bfar;vu32 afsr; scb_typedef; /* system control block structure */

5、它們對應arm手冊中的名稱為cpuid = cpuid base registericsr = interrupt control state registervtor = vector table offset registeraircr = application interrupt/reset control registerscr = system control registerccr = configuration control registershpr = system handlers priority registershcsr = system handler contr

6、ol and state registercfsr = configurable fault status registershfsr = hard fault status registerdfsr = debug fault status registermmfar = mem manage address registerbfar = bus fault address registerafsr = auxiliary fault status register三、系統時鐘寄存器組stm32的固件庫中有如下定義：typedef structvu32 ctrl;vu32 load;vu32 val;vuc32 calib; systick_typedef;它們對應arm手冊中的名稱為ctrl = systick control and status registerload = systick reload value registerval