大連理工大學城市學院 FPGA實驗報告 實驗內容：8位ALU系別班級：電子1004班學號：姓名：日期：2013.4.14 一設計概述： 一種基于可編程邏輯器件FPGA和硬件描述語言的8位的ALU的設計方法。該ALU采用層次設計方法，有寄存器模塊、控制模塊和顯示模塊組成，能實現8位無符號數的取值、加減和4種邏輯運算（與、或、異或、同或）。該ALU在QuartusII軟件環境下進行功能仿真，通過DE2驗證。二 設計功能：1、該處理器的數據寬度為8bit，可以實現算術加法、減法、邏輯與、邏輯或、邏輯非、邏輯與非、邏輯或非和邏輯異或等8種運算。2、用選擇端opcode 2:0 選擇8種運算，2個操作數分別是a_r 7:0和b_r7:0，運算結果是alu_out7:0；并定義選擇如下。選擇端opcode2:0運算結果解釋說明000A操作數a_r7:0001B操作數b_r7:0010算術加法011算術減法100邏輯與101邏輯或110邏輯異或111邏輯同或3、使用DE2板上的3個撥碼開關設置當前ALU的運算功能，再由8個撥碼開關給定數據A和數據B，由一個按鍵key手動提供脈沖。三 設計方案：本設計共有5個模塊。1）脈沖輸出器（key手動脈沖），計數依次產生4個脈沖到各個部件，第一個脈沖啟動信號。2）寄存器A，第二個脈沖來時鎖存數據A，并在數碼管上顯示。3）寄存器B，第三個脈沖來時鎖存數據B，并在數碼管上顯示。4）8位ALU，第四個脈沖來時進行運算，并鎖存結果alu_out。5）結果顯示器，將結果顯示通過DE2上的數碼管顯示。四 程序分析：主程序模塊:module alu8(clk,clk_r,rst,a,b,alu_out,opcode,sw_ab,HEX1, HEX0, HEX7, HEX6, HEX5, HEX4);input clk,rst,clk_r;input 7:0 sw_ab;input 2:0 opcode;output 6:0 HEX1, HEX0, HEX7, HEX6, HEX5, HEX4;output 7:0 a;output 7:0 b;output 7:0 alu_out;rega U1(.clk(clk),.rst(rst),.sw_ab(sw_ab),.a_r(a),.clk_r(clk_r),.HEX7(HEX7),. HEX6(HEX6);regb U2(.clk(clk),.rst(rst),.sw_ab(sw_ab),.b_r(b),.clk_r(clk_r),.HEX5(HEX5),. HEX4(HEX4);alur U3(.clk(clk),.rst(rst),.a_r(a),.b_r(b),.alu_out(alu_out),.opcode(opcode);digital U4(.clk_r(clk_r),.rst(rst),.alu_out(alu_out),.HEX1(HEX1),. HEX0(HEX0);endmodule第一位數A模塊：module rega (clk,clk_r,rst,sw_ab,a_r,HEX7,HEX6);input 7:0 sw_ab;input clk,clk_r,rst;output 7:0 a_r;reg 7:0 a_r;output reg6:0 HEX7,HEX6;reg 3:0 cnt;always (posedge clk or negedge rst)if(!rst) cnt=1d0;else if(cnt=5) cnt=1d0;else cnt=cnt+1d1;always (posedge clk or negedge rst)if(!rst) a_r=0;else if(cnt=1) a_r=sw_ab;else a_r=a_r;parameter seg0=7b1000000,seg1=7b1111001,seg2=7b0100100,seg3=7b0110000,seg4=7b0011001,seg5=7b0010010,seg6=7b0000010,seg7=7b1111000,seg8=7b0000000,seg9=7b0010000,sega=7b0001000,segb=7b0000011,segc=7b1000110,segd=7b0100001,sege=7b0000110,segf=7b0001110;always (posedge clk_r)case(a_r3:0)4h0: HEX66:0=seg0;4h1: HEX66:0=seg1;4h2: HEX66:0=seg2;4h3: HEX66:0=seg3;4h4: HEX66:0=seg4;4h5: HEX66:0=seg5;4h6: HEX66:0=seg6;4h7: HEX66:0=seg7;4h8: HEX66:0=seg8;4h9: HEX66:0=seg9;4ha: HEX66:0=sega;4hb: HEX66:0=segb;4hc: HEX66:0=segc;4hd: HEX66:0=segd;4he: HEX66:0=sege;4hf: HEX66:0=segf;default:HEX66:0=seg0;endcasealways (posedge clk_r)case(a_r7:4)4h0: HEX76:0=seg0;4h1: HEX76:0=seg1;4h2: HEX76:0=seg2;4h3: HEX76:0=seg3;4h4: HEX76:0=seg4;4h5: HEX76:0=seg5;4h6: HEX76:0=seg6;4h7: HEX76:0=seg7;4h8: HEX76:0=seg8;4h9: HEX76:0=seg9;4ha: HEX76:0=sega;4hb: HEX76:0=segb;4hc: HEX76:0=segc;4hd: HEX76:0=segd;4he: HEX76:0=sege;4hf: HEX76:0=segf;default:HEX76:0=seg0;endcaseendmodule第二位數B模塊：module regb (clk,clk_r,rst,sw_ab,b_r,HEX5,HEX4);input 7:0 sw_ab;input clk,clk_r,rst;output 7:0 b_r;reg 7:0 b_r;output reg6:0 HEX5,HEX4;reg 3:0 cnt;always (posedge clk or negedge rst)if(!rst) cnt=1d0;else if(cnt=5) cnt=1d0;else cnt=cnt+1d1;always (posedge clk or negedge rst)if(!rst) b_r=0;else if(cnt=2) b_r=sw_ab;else b_r=b_r;parameter seg0=7b1000000,seg1=7b1111001, seg2=7b0100100,seg3=7b0110000,seg4=7b0011001,seg5=7b0010010,seg6=7b0000010,seg7=7b1111000,seg8=7b0000000,seg9=7b0010000,sega=7b0001000,segb=7b0000011,segc=7b1000110,segd=7b0100001,sege=7b0000110,segf=7b0001110;always (posedge clk_r)case(b_r3:0)4h0: HEX46:0=seg0;4h1: HEX46:0=seg1;4h2: HEX46:0=seg2;4h3: HEX46:0=seg3;4h4: HEX46:0=seg4;4h5: HEX46:0=seg5;4h6: HEX46:0=seg6;4h7: HEX46:0=seg7;4h8: HEX46:0=seg8;4h9: HEX46:0=seg9;4ha: HEX46:0=sega;4hb: HEX46:0=segb;4hc: HEX46:0=segc;4hd: HEX46:0=segd;4he: HEX46:0=sege;4hf: HEX46:0=segf;default:HEX46:0=seg0;endcasealways (posedge clk_r)case(b_r7:4)4h0: HEX56:0=seg0;4h1: HEX56:0=seg1;4h2: HEX56:0=seg2;4h3: HEX56:0=seg3;4h4: HEX56:0=seg4;4h5: HEX56:0=seg5;4h6: HEX56:0=seg6;4h7: HEX56:0=seg7;4h8: HEX56:0=seg8;4h9: HEX56:0=seg9;4ha: HEX56:0=sega;4hb: HEX56:0=segb;4hc: HEX56:0=segc;4hd: HEX56:0=segd;4he: HEX56:0=sege;4hf: HEX56:0=segf;default:HEX56:0=seg0;endcaseendmodule運算模塊：module alur(clk,rst,alu_out,a_r,b_r,opcode,zero);output 7:0 alu_out;output zero;input 7:0 a_r,b_r;input 2:0 opcode;input clk,rst;reg 7:0 alu_out;reg 3:0 cnt;parameter quA=3b000,quB=3b001,ADD=3b010,DEC=3b011,ANDD=3b100,XORR=3b101,XOR=3b110,NXOP=3b111;assign zero=!a_r;always (posedge clk or negedge rst)if(!rst) cnt=1d0;else if(cnt=5) cnt=1d0;else cnt=cnt+1d1;always (posedge clk or negedge rst)if(!rst) alu_out=0;else if(cnt=3) begincasex(opcode)quA: alu_out=a_r;quB: alu_out=b_r;ADD: alu_out=a_r+b_r;DEC: alu_out=a_r-b_r;ANDD: alu_out=a_r&b_r;XORR: alu_out=a_r|b_r;XOR: alu_out=a_rb_r;NXOP: alu_out=a_rb_r;default: alu_out=8bxxxx_xxxx;endcaseendelse alu_out=0;endmodule結果顯示模塊：module digital(clk_r,rst,alu_out,HEX1,HEX0);input 7:0 alu_out;input clk_r,rst;output reg6:0 HEX1,HEX0;parameter seg0=7b1000000,seg1=7b1111001, seg2=7b0100100,seg3=7b0110000,seg4=7b0011001,seg5=7b0010010,seg6=7b0000010,seg7=7b1111000,seg8=7b0000000,seg9=7b0010000,sega=7b0001000,segb=7b0000011,segc=7b1000110,segd=7b0100001,sege=7b0000110,segf=7b0001110;always (posedge clk_r)case(alu_out3:0)4h0: HEX06:0=seg0;4h1: HEX06:0=seg1;4h2: HEX06:0=seg2;4h3: HEX06:0=seg3;4h4: HEX06:0=seg4;4h5: HEX06:0=seg5;4h6: HEX06:0=seg6;4h7: HEX06:0=seg7;4h8: HEX06:0=seg8;4h9: HEX06:0=seg9;4ha: HEX06:0=sega;4hb: HEX06:0=segb;4hc: HEX06:0=segc;4hd: HEX06:0=segd;4he: HEX06:0=sege;4hf: HEX06:0=segf;default: HEX06:0=seg0;endcasealways (posedge clk_r)case(alu_out7:4)4h0: HEX16:0=seg0;4h1: HEX16:0=seg1;4h2: HEX16:0=seg2;4h3: HEX16:0=seg3;4h4: HEX16:0=seg4;4h5: HEX16:0=seg5;4h6: HEX16:0=seg6;4h7: HEX16:0=seg7;4h8: HEX16:0=seg8;4h