1、 EDA技術實驗報告冊班級：姓名：學號：指導教師：開課時間: 2013 至2014 學年第 1 學期16 / 18實驗名稱交通燈信號控制設計實驗時間2013年12月05日姓 名實驗成績一、實驗目的1.掌握VHDL語言的基本結構。2.掌握VHDL層次化的設計方法。3.掌握VHDL基本邏輯電路的綜合設計應用。二、實驗設備計算機軟件：Quartus IIEDA實驗箱。主芯片：EPM7128SLC84-15或EP1K100QC208-3。下載電纜，導線等。三、實驗容設計并調試好一個由一條主干道和一條支干道的匯合點形成的十字交叉路口的交通燈控制器，具體要求如下：1.主、支干道各設一個綠、黃、紅指示燈，兩

2、個顯示數碼管。2.主干道處于常允許通行狀態，而支干道有車來時才允許通行。當主干道允許通行亮綠燈時，支干道亮紅燈。而支干道允許通行亮綠燈時，主干道亮紅燈。3.當主、支干道均有車時，兩者交替允許通行，主干道每次放行45S，支干道每次放行25S，在每次由亮綠燈變成亮紅燈的轉換過程中，要亮5S的黃燈作為過渡，并進行減計時顯示。要求編寫交通燈控制器電路邏輯圖中的各個模塊的VHDL語言程序，并完成交通燈控制器的頂層設計，然后利用開發工具軟件對其進行編譯和仿真，最后要通過實驗開發系統對其進行硬件驗證。（一）編寫交通燈控制器JTDKZ模塊的VHDL程序，并對其進行編譯和仿真，初步驗證設計的正確性。LIBRAR

3、Y IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JTDKZ ISPORT(CLK, SM, SB: IN STD_LOGIC;MR, MY, MG, BR, BY, BG: OUT STD_LOGIC);END ENTITY JTDKZ;ARCHITECTURE ART OF JTDKZ ISTYPE STATE_TYPE IS(A, B, C, D);SIGNALSTATE: STATE_TYPE;signalt:integer range 0 to 45;BEGIN PROCESS(CLK) ISBEGINIF(CLK'EVENT AND CLK

4、='1')THENCASESTATE IS WHEN A=> IF(SB AND SM)='1' THENIF CNT=44 THEN CNT<=0; STATE<=B;ELSE CNT<=CNT+1;STATE<=A; END IF; ELSIF(SB AND (NOT SM)='1' THENSTATE<=B; CNT<=0; ELSE STATE<=A; CNT<=0; END IF; WHEN B=> IF CNT=4 THEN CNT<=0;STATE<=C; EL

5、SE CNT<=CNT+1;STATE<=B; END IF; WHEN C=> IF(SM AND SB)='1' THEN IF CNT=24 THEN CNT<=0; STATE<=D; ELSE CNT<=CNT+1;STATE<=C; END IF; ELSIF SB='0' THEN STATE<=D; CNT<=0; ELSE STATE<=C; CNT<=0; END IF;WHEN D=> IF CNT=4 THEN CNT<=0; STATE<=A; ELSE

6、 CNT<=CNT+1;STATE<=D; END IF;END CASE;END IF;END PROCESS ; RGY:PROCESS(STATE) ISBEGINCASESTATE ISWHEN A=>MR<='0' MY<='0' MG<='1'BR<='1' BY<='0' BG<='0'WHEN B=>MR<='0' MY<='1' MG<='0'BR<=

7、'1' BY<='0' BG<='0'WHEN C=>MR<='1' MY<='0' MG<='0'BR<='0' BY<='0' BG<='1'WHEN D=>MR<='1' MY<='0' MG<='0'BR<='0' BY<='1' BG<='0'END C

8、ASE; END PROCESS RGY;END ARCHITECTURE ART;（二）編寫45S定時單元CNT45S模塊的VHDL程序，并對其進行編譯和仿真，初步驗證設計的正確性。-45s定時模塊源程序CNT45S.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY time_45s IS PORT(SB,SM, CLK, EN45: IN STD_LOGIC; DOUT45M, DOUT45B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); EN

9、D ENTITY time_45s ; ARCHITECTURE ART OF time_45s IS SIGNAL CNT6B: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN PROCESS(SB, SM, CLK, EN45) IS BEGIN IF(CLK'EVENT AND CLK= '1')THEN IF SB='1' AND SM='1' THEN IF EN45='1'THEN CNT6B<=CNT6B+1;ELSE CNT6B<="000000" E

10、ND IF; ELSE CNT6B<="000000" END IF; END IF; END PROCESS; PROCESS(CNT6B) IS BEGIN CASE CNT6B IS WHEN "000000"=>DOUT45M<="01000101" DOUT45B<="01010000" -BCD數45, 50 WHEN "000001"=>DOUT45M<="01000100" DOUT45B<="0100100

11、1" -BCD數44, 49 WHEN "000010"=>DOUT45M<="01000011" DOUT45B<="01001000" -BCD數43, 48 WHEN "000011"=>DOUT45M<="01000010" DOUT45B<="01000111" -BCD數42, 48 WHEN "000100"=>DOUT45M<="01000001" DOUT45B

12、<="01000110" -BCD數41, 50 WHEN "000101"=>DOUT45M<="01000000" DOUT45B<="01000101" -BCD數40, 49 WHEN "000110"=>DOUT45M<="00111001" DOUT45B<="01000100" -BCD數39, 48 WHEN "000111"=>DOUT45M<="0011

13、1000" DOUT45B<="01000011" -BCD數38, 48 WHEN "001000"=>DOUT45M<="00110111" DOUT45B<="01000010" -BCD數37, 50 WHEN "001001"=>DOUT45M<="00110110" DOUT45B<="01000001" -BCD數36, 49 WHEN "001010"=>DOUT

14、45M<="00110101" DOUT45B<="01000000" -BCD數35, 48 WHEN "001011"=>DOUT45M<="00110100" DOUT45B<="00111001" -BCD數34, 48 WHEN "001100"=>DOUT45M<="00110011" DOUT45B<="00111000" -BCD數33, 50 WHEN "001

15、101"=>DOUT45M<="00110010" DOUT45B<="00110111" -BCD數32, 49 WHEN "001110"=>DOUT45M<="00110001" DOUT45B<="00110110" -BCD數31, 48 WHEN "001111"=>DOUT45M<="00110000" DOUT45B<="00110101" -BCD數30,

16、 48 WHEN "010000"=>DOUT45M<="00101001" DOUT45B<="00110100" -BCD數29, 50 WHEN "010001"=>DOUT45M<="00101000" DOUT45B<="00110011" -BCD數28, 49 WHEN "010010"=>DOUT45M<="00100111" DOUT45B<="00110

17、010" -BCD數27, 48 WHEN "010011"=>DOUT45M<="00100110" DOUT45B<="00110001" -BCD數26, 48 WHEN "010100"=>DOUT45M<="00100101" DOUT45B<="00110000" -BCD數25, 50 WHEN "010101"=>DOUT45M<="00100100" DOUT4

18、5B<="00101001" -BCD數24, 49 WHEN "010110"=>DOUT45M<="00100011" DOUT45B<="00101000" -BCD數23, 48 WHEN "010111"=>DOUT45M<="00100010" DOUT45B<="00100111" -BCD數22, 48 WHEN "011000"=>DOUT45M<="00

19、100001" DOUT45B<="00100110" -BCD數21, 50 WHEN "011001"=>DOUT45M<="00100000" DOUT45B<="00100101" -BCD數20, 49 WHEN "011010"=>DOUT45M<="00011001" DOUT45B<="00100100" -BCD數19, 48 WHEN "011011"=>DO

20、UT45M<="00011000" DOUT45B<="00100011" -BCD數18, 48 WHEN "011100"=>DOUT45M<="00010111" DOUT45B<="00100010" -BCD數17, 50 WHEN "011101"=>DOUT45M<="00010110" DOUT45B<="00100001" -BCD數16, 49 WHEN "0

21、11110"=>DOUT45M<="00010101" DOUT45B<="00100000" -BCD數15, 48 WHEN "011111"=>DOUT45M<="00010100" DOUT45B<="00011001" -BCD數14, 48 WHEN "100000"=>DOUT45M<="00010011" DOUT45B<="00011000" -BCD數1

22、3, 50 WHEN "100001"=>DOUT45M<="00010010" DOUT45B<="00010111" -BCD數12, 49 WHEN "100010"=>DOUT45M<="00010001" DOUT45B<="00010110" -BCD數11, 48 WHEN "100011"=>DOUT45M<="00010000" DOUT45B<="000

23、10101" -BCD數10, 48 WHEN "100100"=>DOUT45M<="00001001" DOUT45B<="00010100" -BCD數9, 50 WHEN "100101"=>DOUT45M<="00001000" DOUT45B<="00010011" -BCD數8, 49 WHEN "100110"=>DOUT45M<="00000111" DOUT4

24、5B<="00010010" -BCD數7, 48 WHEN "100111"=>DOUT45M<="00000110" DOUT45B<="00010001" -BCD數6, 48 WHEN "101000"=>DOUT45M<="00000101" DOUT45B<="00010000" -BCD數5, 50 WHEN "101001"=>DOUT45M<="00000

25、100" DOUT45B<="00001001" -BCD數4, 49 WHEN "101010"=>DOUT45M<="00000011" DOUT45B<="00001000" -BCD數3, 48 WHEN "101011"=>DOUT45M<="00000010" DOUT45B<="00000111" -BCD數2, 07 WHEN "101100"=>DOUT45M&

26、lt;="00000001" DOUT45B<="00000110" -BCD數1, 06 WHEN OTHERS=>DOUT45M<="00000000" DOUT45B<="00000000" -BCD數00, 00 END CASE; END PROCESS; END ARCHITECTURE ART;（三）編寫25S定時單元CNT25S模塊的VHDL程序，并對其進行編譯和仿真，初步驗證設計的正確性。-25s定時模塊源程序CNT25S.VHD LIBRARY IEEE; USE IEE

27、E.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY time_25s IS PORT(SB, SM, CLK, EN25: IN STD_LOGIC; DOUT25M, DOUT25B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END ENTITY time_25s; ARCHITECTURE ART OF time_25s IS SIGNAL CNT_5Bit: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN PROCESS(SB, SM, CLK, EN25) IS

28、BEGIN IF SB='0' OR SM='0' THEN CNT_5Bit<="00000" ELSIF(CLK'EVENT AND CLK= '1')THEN IF EN25='1' THEN CNT_5Bit<=CNT_5Bit+1; ELSIF EN25='0'THEN CNT_5Bit<="00000" END IF; END IF; END PROCESS; PROCESS(CNT_5Bit) IS BEGIN CASE CNT_5Bi

29、t IS WHEN "00000"=>DOUT25B<="00100101" DOUT25M<="00110000" -BCD數25, 50 WHEN "00001"=>DOUT25B<="00100100" DOUT25M<="00101001" -BCD數24, 49 WHEN "00010"=>DOUT25B<="00100011" DOUT25M<="0010100

30、0" -BCD數23, 48 WHEN "00011"=>DOUT25B<="00100010" DOUT25M<="00100111" -BCD數22, 48 WHEN "00100"=>DOUT25B<="00100001" DOUT25M<="00100110" -BCD數21, 50 WHEN "00101"=>DOUT25B<="00100000" DOUT25M<

31、;="00100101" -BCD數20, 49 WHEN "00110"=>DOUT25B<="00011001" DOUT25M<="00100100" -BCD數19, 48 WHEN "00111"=>DOUT25B<="00011000" DOUT25M<="00100011" -BCD數18, 48 WHEN "01000"=>DOUT25B<="00010111&q

32、uot; DOUT25M<="00100010" -BCD數17, 50 WHEN "01001"=>DOUT25B<="00010110" DOUT25M<="00100001" -BCD數16, 49 WHEN "01010"=>DOUT25B<="00010101" DOUT25M<="00100000" -BCD數15, 48 WHEN "01011"=>DOUT25B<=&

33、quot;00010100" DOUT25M<="00011001" -BCD數14, 48 WHEN "01100"=>DOUT25B<="00010011" DOUT25M<="00011000" -BCD數13, 50 WHEN "01101"=>DOUT25B<="00010010" DOUT25M<="00010111" -BCD數12, 49 WHEN "01110"=&g

34、t;DOUT25B<="00010001" DOUT25M<="00010110" -BCD數11, 48 WHEN "01111"=>DOUT25B<="00010000" DOUT25M<="00010101" -BCD數10, 48 WHEN "10000"=>DOUT25B<="00001001" DOUT25M<="00010100" -BCD數9, 50 WHEN "

35、10001"=>DOUT25B<="00001000" DOUT25M<="00010011" -BCD數8, 49 WHEN "10010"=>DOUT25B<="00000111" DOUT25M<="00010010" -BCD數7, 48 WHEN "10011"=>DOUT25B<="00000110" DOUT25M<="00010001" -BCD數6, 48

36、 WHEN "10100"=>DOUT25B<="00000101" DOUT25M<="00010000" -BCD數5, 50 WHEN "10101"=>DOUT25B<="00000100" DOUT25M<="00001001" -BCD數4, 49 WHEN "10110"=>DOUT25B<="00000011" DOUT25M<="00001000"

37、; -BCD數3, 48WHEN "10111"=>DOUT25B<="00000010" DOUT25M<="00000111" -BCD數2, 07 WHEN "11000"=>DOUT25B<="00000001" DOUT25M<="00000110" -BCD數1, 06 WHEN OTHERS =>DOUT25B<="00000000" DOUT25M<="00000000&quo

38、t; -BCD數00, 00 END CASE; END PROCESS; END ARCHITECTURE ART;（四）編寫5S定時單元CNT05S模塊的VHDL程序，并對其進行編譯和仿真，初步驗證設計的正確性。-5s定時模塊源程序CNT05S.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY time_5s IS PORT(CLK, EN05M, EN05B: IN STD_LOGIC; DOUT5: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

39、; END ENTITY time_5s; ARCHITECTURE ART OF time_5s IS SIGNAL CNT_3Bit: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN PROCESS(CLK, EN05M, EN05B) IS BEGIN IF(CLK'EVENT AND CLK= '1')THEN IF EN05M='1' OR EN05B='1' THEN CNT_3Bit<=CNT_3Bit+1; ELSE CNT_3Bit<="000" END IF; E

40、ND IF; END PROCESS; PROCESS(CNT_3Bit) IS BEGIN CASE CNT_3Bit IS WHEN "000" =>DOUT5<="00000101" -BCD數05 WHEN "001" =>DOUT5<="00000100" -BCD數04 WHEN "010" =>DOUT5<="00000011" -BCD數03 WHEN "011" =>DOUT5<="

41、;00000010" -BCD數02 WHEN "100" =>DOUT5<="00000001" -BCD數01 WHEN OTHERS=>DOUT5<="00000000" -BCD數00 END CASE; END PROCESS; END ARCHITECTURE ART;（五）編寫顯示控制單元XSKZ模塊的VHDL程序，并對其進行編譯和仿真，初步驗證設計的正確性。-顯示控制模塊源程序XSKZ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE

42、 IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY XSKZ IS PORT(EN45, EN25, EN05M, EN05B:IN STD_LOGIC; AIN45M, AIN45B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); AIN25M, AIN25B, AIN05: IN STD_LOGIC_VECTOR(7 DOWNTO 0); dec_m, dec_b: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END ENTITY XSKZ; ARCHITECTURE ART OF XSKZ IS BEGIN PROCESS

43、(EN45,EN25,EN05M, EN05B,AIN45M,AIN45B,AIN05,AIN25M,AIN25B) IS BEGIN IF EN45='1' THEN dec_m<=AIN45M(7 DOWNTO 0); dec_b<=AIN45B(7 DOWNTO 0); ELSIF EN05M='1' THEN dec_m<=AIN05(7 DOWNTO 0); dec_b<=AIN05(7 DOWNTO 0); ELSIF EN25='1' THEN dec_m<=AIN25M(7 DOWNTO 0); de

44、c_b<=AIN25B(7 DOWNTO 0); -ELSIF EN05B='1' THEN ELSE dec_m<=AIN05(7 DOWNTO 0); dec_b<=AIN05(7 DOWNTO 0); END IF; END PROCESS; END ARCHITECTURE ART; （六）數碼管動態掃描顯示電路設計LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY disp_sc

45、an IS PORT(CLK_scan: IN STD_LOGIC; DEC_M: IN STD_LOGIC_VECTOR(7 DOWNTO 0); DEC_B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); LEDW: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); SEG7: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END ENTITY disp_scan; ARCHITECTURE ART OF disp_scan ISsignal temp: STD_LOGIC_VECTOR(3 DOWNTO 0);signal CN

46、T:STD_LOGIC_VECTOR(2 DOWNTO 0); begin PROCESS(CLK_scan) IS BEGIN IF CLK_scan'EVENT AND CLK_scan='1' THEN IF CNT="111" THEN CNT<="000" ELSE CNT<=CNT+'1' END IF; END IF; END PROCESS; LEDW<=CNT; PROCESS(CNT,TEMP,DEC_B,DEC_M) IS BEGIN CASE CNT IS WHEN &qu

47、ot;000" => TEMP<=DEC_M(7 DOWNTO 4); WHEN "001" => TEMP<=DEC_M(3 DOWNTO 0); WHEN "110" => TEMP<=DEC_B(7 DOWNTO 4); WHEN "111" => TEMP<=DEC_B(3 DOWNTO 0); WHEN OTHERS=> TEMP<="1111" END CASE; CASE TEMP IS WHEN "0000"=

48、> SEG7<="00111111" WHEN "0001"=> SEG7<="00000110" WHEN "0010"=> SEG7<="01011011" WHEN "0011"=> SEG7<="01001111" WHEN "0100"=> SEG7<="01100110" WHEN "0101"=> SEG7<=&

49、quot;01101101" WHEN "0110"=> SEG7<="01111101" WHEN "0111"=> SEG7<="00000111" WHEN "1000"=> SEG7<="01111111" WHEN "1001"=> SEG7<="01101111" WHEN OTHERS=> SEG7<="00000000" END C

50、ASE; END PROCESS; END ARCHITECTURE ART;（七）利用前面所設計的模塊，完成交通燈信號控制器的頂層設計，并對其進行編譯和仿真，初步驗證設計的正確性。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY traffic ISPORT(SB,SM, CLK, clk_scan: IN STD_LOGIC;MR1,MY1,MG1,BR1,BY1,BG1:BUFFER STD_LOGIC;-MR2,MY2,MG2,BR2,BY2,BG2:OUT STD_LOGIC;ledw:out STD_LOGIC_VECTOR(2 DOW

51、NTO 0);seg7: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY traffic ;ARCHITECTURE ART OF traffic ISCOMPONENT JTDKZ ISPORT(CLK, SM, SB: IN STD_LOGIC;MR, MY, MG, BR, BY, BG: OUT STD_LOGIC);END COMPONENT JTDKZ; COMPONENT time_45s IS PORT(SB,SM, CLK, EN45: IN STD_LOGIC; DOUT45M, DOUT45B: OUT STD_LOGIC_VECT

52、OR(7 DOWNTO 0); END COMPONENT time_45s ; COMPONENT time_25s IS PORT(SB, SM, CLK, EN25: IN STD_LOGIC; DOUT25M, DOUT25B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT time_25s;COMPONENT time_5s IS PORT(CLK, EN05M, EN05B: IN STD_LOGIC; DOUT5: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT time_5s; C

53、OMPONENT XSKZ IS PORT(EN45, EN25, EN05M, EN05B:IN STD_LOGIC; AIN45M, AIN45B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); AIN25M, AIN25B, AIN05: IN STD_LOGIC_VECTOR(7 DOWNTO 0); dec_m, dec_b: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT XSKZ; COMPONENT disp_scan IS PORT(CLK_scan: IN STD_LOGIC; DEC_M: IN STD_LOGIC_VECTOR(7 DOWNTO 0); DEC_B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); LEDW: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); SEG7: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT disp_scan; SIGNAL DATA_45M: STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL DATA_45B: S