1、矽製程被動元件之設計與特性分析及其在射頻積體電路上之應用Design and Characterization of Passive Components in Silicon-Based Process and Their Application in RFICs國科會計畫編號： NSC 92-2218-E-009 015 IC 編號：U18-93A-10t指導教授：林育德 交通大學電信系教授電話：(03)5712121-54530 E-mail: .tw設計者：許伯驊 碩士班研究生電話：(03)5712121-54593 E-mail: diskman.cm

2、91.tw 一、 中文摘要(及關鍵字)對於RF CMOS 電感來說，如何降低與有損耗的矽基板的耦合效應或增加與之隔絕度(Isolation)是一重大課題，本案的方法是在電感中加入一去磁耦合器，以去除矽基板中之渦電流。另外，本文亦利用類似傳統微波電路週期結構的觀念，提出高感值共面結構傳輸線(highly dispersive CPW transmission line)。AbstractIn contrast to the testkey inductors we taped out last time, now we have a great new ideal about

3、the reduction of silicon substrate loss. We present some novel patterns, which are called magnetic decoupler, locate central and beneath the inductor, to reduce eddy current induced in the silicon substrate and elevate Q value very effectively. We propose another designing concept that can decrease

4、inductor area and boost up VLSI circuit density very much more.Keyword: magnetic decoupler二、 研究動機與目的對於積體電路的環境而言，差動型操作(differential operation)可有效隔絕及減低來自於基板的損耗和雜訊，所以明顯優於單端式操作(single ended)。而積體電路多層金屬的特性，利用其中最上面幾層金屬用via 連結在一起，可有效降低導體損耗，或是在不同金屬層間繞圈，可大幅節省面積。有鑑於此，本人將致力於3D對稱型電感之研發。此種電感可應用於任何形式之射頻積體電路（26GHz）

5、。三、 研究方法與成果3.1設計原理與方法使用Ansoft HFSS作3D的電磁模擬。需注意的參數有線寬、線距、外徑，使用金屬層等。因高頻操作(2.GHz)集膚深度(skin depth)約2.7um左右，電流大部分集中在導體兩側，換言之，徒增線寬對改善電感Q值沒有多少幫助。另外線距若太小降低自振頻率，故本案之電感線寬固定10um，線距固定5um。 3.2元件原理及架構介紹本案之電感皆為四層金屬用via連接之一圈電感，在電感中加入不同pattern之去磁耦合器，比較它們對矽基板耦合隔絕度之貢獻。3.3量測結果佈局裡加了open的dummy pads作de-embedding。De-embede

6、d Process:_YdeY=Y Yde transforms to Sde or ZdeQ=Im(Zin)/Re(Zin), L=Im(Zin)/(2f)因die photo 不甚清楚，故以layout 代替。1.Prototype ( No. md_ind1)2.Squre hole magnetic decoupler (No. md_ind2) 3.Circular hole magnetic decoupler (No. md_ind3)4. Inductive magnetic decoupler (No. md_ind4)5. Highly dispersive CPW tra

7、nsmission line (No. hd_trl)四、 模型建立與量測結果比較使用的電感等效模型示於下圖，量測結果的模型的粹取列於表二，所使用的軟體為ADS。請參考model.doc，裡面有相當詳細的說明。五、 結論本次下線的重點為如何以最低的成本有效降低矽基板損耗，透過模擬結果得知在電感中設計一個去磁耦合器是有效的方法，原理就是擾亂原電感產生的渦電流，另一重點是利用highly dispersive 或是 slow wave 的觀念，設計高感值的CPW transmission line，其面積為同感值之一般電感約1/20。六、.參考文獻：1 C. P. Yue and S. S. Wo

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13、Custom Integrated Circuits Conference, pp.419-422, 2002.11 B. Razavi, “Design of Inegrated Circuits for Optical Communications”, published by McGraw Hill,2003.12 M. Danesh, J. R. Long, R. A. Hadaway and D.L. Harame, “A Q-Factor Enhancement Technique for MMIC Inductors,” IEEE MTT-s Digest, 1998.* Chip Features CKT name : 0.18um微型3D對稱型電感Testkey DesignCAD Tools: Ansoft HFSS, Agilent ADSTech