1、第四章 邏輯門電路（Logic Gates Circuits）1知識(shí)要點(diǎn)CMOS邏輯電平和噪聲容限；CMOS邏輯反相器、與非門、或非門、非反相門、與或非門電路的結(jié)構(gòu)；CMOS邏輯電路的穩(wěn)態(tài)電氣特性：帶電阻性負(fù)載的電路特性、非理想輸入時(shí)的電路特性、負(fù)載效應(yīng)、不用的輸入端及等效的輸入/輸出電路模型；動(dòng)態(tài)電氣特性：轉(zhuǎn)換時(shí)間、傳輸延遲、電流尖峰、扇出特性；特殊的輸入/輸出電路結(jié)構(gòu)：CMOS傳輸門、三態(tài)輸出結(jié)構(gòu)、施密特觸發(fā)器輸入結(jié)構(gòu)、漏極開路輸出結(jié)構(gòu)。重點(diǎn)：1CMOS邏輯門電路的結(jié)構(gòu)特點(diǎn)及與邏輯表達(dá)式的對(duì)應(yīng)關(guān)系；2CMOS邏輯電平的定義和噪聲容限的計(jì)算；3邏輯門電路扇出的定義及計(jì)算；4邏輯門電路轉(zhuǎn)換時(shí)間

2、、傳輸延遲的定義。難點(diǎn)：1CMOS互補(bǔ)網(wǎng)絡(luò)結(jié)構(gòu)的分析和設(shè)計(jì)；2邏輯門電路對(duì)負(fù)載的驅(qū)動(dòng)能力的計(jì)算。（1）PMOS和NMOS場(chǎng)效應(yīng)管的開關(guān)特性MOSFET管實(shí)際上由4部分組成：Gate，Source，Drain和Backgate，Source和Drain之間由Backgate連接，當(dāng)Gate對(duì)Backgate的電壓超過某個(gè)值時(shí)，Source和Drain之間的電介質(zhì)就會(huì)形成一個(gè)通道，使得兩者之間產(chǎn)生電流，從而導(dǎo)通管子，這個(gè)電壓值稱為閾值電壓。對(duì)PMOS管而言，閾值電壓是負(fù)值，而對(duì)NMOS管而言，閾值電壓是正值。也就是說，在邏輯電路中，NMOS管和PMOS管均可看做受控開關(guān)，對(duì)于高電平1，NMOS導(dǎo)通

3、，PMOS截?cái)?；對(duì)于低電平0，NMOS截?cái)啵琍MOS導(dǎo)通。（2）CMOS門電路的構(gòu)成規(guī)律每個(gè)CMOS門電路都由NMOS電路和PMOS電路兩部分組成，并且每個(gè)輸入都同時(shí)加到一個(gè)NMOS管和一個(gè)PMOS管的柵極（Gate）上。對(duì)正邏輯約定而言，NMOS管的串聯(lián)（Series Connection）可實(shí)現(xiàn)與操作（Implement AND Operation），并聯(lián)（Parallel Connection）可實(shí)現(xiàn)或操作（Implement OR Operation）。PMOS電路與NMOS電路呈對(duì)偶關(guān)系，即當(dāng)NMOS管串聯(lián)時(shí)，其相應(yīng)的PMOS管一定是并聯(lián)的；而當(dāng)NMOS管并聯(lián)時(shí)，其相應(yīng)的PMOS管

4、一定需要串聯(lián)。基本邏輯關(guān)系體現(xiàn)在NMOS管的網(wǎng)絡(luò)上，由于NMOS網(wǎng)絡(luò)接地，輸出需要反相（取非）。（3）CMOS邏輯電路的穩(wěn)態(tài)電氣特性 一般來說，器件參數(shù)表中用以下參數(shù)來說明器件的邏輯電平定義：VOHmin 輸出為高電平時(shí)的最小輸出電壓VIHmin 能保證被識(shí)別為高電平時(shí)的最小輸入電壓VOLmax 能保證被識(shí)別為低電平時(shí)的最大輸入電壓VILmax 輸出為低電平時(shí)的最大輸出電壓不同邏輯種類對(duì)應(yīng)的參數(shù)值不同。輸入電壓主要由晶體管的開關(guān)門限電壓決定，而輸出電壓主要由晶體管的“導(dǎo)通”電阻決定。噪聲容限是指芯片在最壞輸出電壓情況下，多大的噪聲電平會(huì)使得輸出電壓被破壞成不可識(shí)別的輸入值。對(duì)于輸出是高電平的情

5、況，其最壞的輸出電壓是VOHmin，如果要使該電壓能在輸入端被正確識(shí)別為高電平，即被噪聲污染后的電壓值應(yīng)該不小于VIHmin，則噪聲容限為VOHmin-VIHmin。對(duì)于輸出是低電平的情況，噪聲容限為VILmax -VOLmax。輸出電流的定義如下。IOLmax：輸出低態(tài)且仍能維持輸出電壓不大于VOLmax時(shí)，輸出端能吸收的最大電流；IOHmax：輸出高態(tài)且仍能維持輸出電壓不小于VOHmin時(shí)，輸出端可提供的最大電流。（4）扇出邏輯門的扇出（fanout）是指該門電路在不超出其最壞情況負(fù)載規(guī)格的條件下能驅(qū)動(dòng)的輸入端的個(gè)數(shù)。扇出不僅依賴于輸出端的特性，還依賴于它驅(qū)動(dòng)的輸入端的特性。扇出的計(jì)算必須

6、考慮輸出的兩種可能狀態(tài)：高電平狀態(tài)和低電平狀態(tài)。直流扇出能力的計(jì)算方法為：最大輸出電流/最大輸入電流。一個(gè)門電路的高電平扇出和低電平扇出不一定相等。通常，門電路的總扇出應(yīng)為高電平扇出和低電平扇出中的較小值。（5）CMOS電路的動(dòng)態(tài)特性轉(zhuǎn)換時(shí)間可分為輸出上升時(shí)間tr和輸出下降時(shí)間tf，其值的大小和門的導(dǎo)通電阻與負(fù)載電容之積成正比。傳輸延遲時(shí)間tp指的是從輸入變化到輸出變化所需的時(shí)間。其值取決于器件內(nèi)部的結(jié)構(gòu)與信號(hào)傳輸?shù)穆窂剑煌粋€(gè)器件，不同輸入/輸出間的傳輸延遲可能不同，由多種因素決定。（6）CMOS電路的功耗輸出不變時(shí)的CMOS電路功耗稱為靜態(tài)功耗。CMOS電路在狀態(tài)轉(zhuǎn)換時(shí)消耗的電能稱為動(dòng)態(tài)功

7、耗，其來源是輸出端上的電容性負(fù)載CL，輸出從低到高轉(zhuǎn)換時(shí)，電流流過P溝道晶體管給負(fù)載充電，類似地，輸出從高到低轉(zhuǎn)換時(shí)，電流流過N溝道晶體管給負(fù)載放電，這兩種情況下晶體管導(dǎo)通的電阻都消耗功率。充電開始時(shí)電壓變化為VDD，結(jié)束時(shí)電壓變化很小，故平均電壓變化為VDD/2，則每次轉(zhuǎn)換消耗的電能為，若每秒鐘變化2f次，則由電容性負(fù)載引起的動(dòng)態(tài)功耗為。2Exercises 4.1 The Stub Series Terminalted low Voltage(SSTV) logic family, used for SDRAM modules, defines a LOW signal to be in

8、the range 0.00.7V, and a HIGH signal to be in the range 1.72.5V. Under a positive-logic convention, indicate the logic value associated with each of the following signal levels:(a) 0.0V(b) 0.7V(c) 1.7V(d) -0.6V (e) 1.6V(f) -2.0V(g) 2.5V(h) 3.3V4.2 Repeat exercise 4.1 using a negative-logic conventio

9、n.4.3 True or false: For a given set of input values, a NAND gate produces the opposite output as a NOR gate.4.4 For a given silicon area, which is likely to be faster, a CMOS NAND gate or a CMOS NOR?4.5 Which has fewer transistors, a CMOS inverting gate or a noninverting gate?4.6 For each of the fo

10、llowing resistive loads, determine whether the output drive specifications of the 74HC00 over the commercial operating range are exceeded (use V= 0.33V，VOHmin = 3.84V and VCC = 5.0 V). You may not exceed IOLmax (4mA) or IOHmax (4mA) in any state.(1) 1.2k W to VCC and 820 W to GND(2) 470 W to VCC and

11、 470 W to GND4.7 A particular Schmitt-trigger inverter has = 0.8 V, = 2.0 V, =1.7 V, and = 1.2 V. How much hysteresis does it have? 4.8 Discuss the pros and cons of larger versus smaller pull-up resistors for open-drain CMOS outputs.4.9 How many diodes are required for an n-input diode AND gate?4.10

12、 Compute the maximum fanout for each of the following cases of a TTL output driving multiple TTL inputs. Also indicate how much “excess” driving capability is available in the LOW or HIGH state for each case. ( Refer to datasheets in Appendix )(1) 74LS driving 74AS (2) 74LS driving 74F 4.11 Compute

13、the LOW-state and HIGH-state DC noise margins for each of the following cases of a TTL-compatible CMOS output driving a TTL input, or vice versa. ( Refer to datasheets in Appendix )(1) 74HCT driving 74LS(2) 74ALS driving 74HCT4.12 Compute the maximum fanout for each of the following case of a TTL-co

14、mpatible CMOS output driving multiple inputs in a TTL logic family. Also indicate how much “excess” driving capability is available in the LOW or HIGH state for each case. ( Refer to datasheets in Appendix )(1) 74HCT driving 74LS(2) 74AHCT driving 74SOptions4.13 Draw a circuit diagram, function table, and logic symbol for a CMOS gate with two inputs A and B and an output Z, where Z = 1 if A = 0 and B = 1, and Z = 0 otherwise (Hint: Only six transistors are