1、VHDL程序設計題四、 編程題（共50分）1、請補全以下二選一VHDL程序（本題10分）Entity mux isport(d0,d1,sel:in bit;q:out BIT ); (2)end mux;architecture connect of MUX is (4) signal tmp1, TMP2 ,tmp3:bit; (6)begin cale:block begin tmp1<=d0 and sel; tmp2<=d1 and (not sel) tmp3<= tmp1 and tmp2;q <= tmp3; (8) end block cale; en

2、d CONNECT ; (10)2、編寫一個2輸入與門的VHDL程序，請寫出庫、程序包、實體、構造體相關語句，將端口定義為標準邏輯型數據結構（本題10分）&abyLIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; （2） ENTITY nand2 IS PORT (a，b:IN STD_LOGIC; （4） y:OUT STD_LOGIC); （6） END nand2; ARCHITECTURE nand2_1 OF nand2 IS （8） BEGIN y <= a NAND b; -與y <=NOT( a AND b);等價 （10）

3、 END nand2_1;3、根據下表填寫完成一個3-8線譯碼器的VHDL程序（16分）。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decoder_3_to_8 IS PORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC; y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); （2）END decoder_3_to_8;ARCHITECTURE rtl OF decoder_3_to_8 IS SIGNAL indata:STD_LOGIC_VECTOR (2 DOWNTO 0);（4）BEGIN ind

4、ata <= c & b & a;（6）PROCESS (indata,g1,g2a,g2b) BEGIN IF (g1 = '1' AND g2a = '0' AND g2b = '0' ) THEN （8） CASE indata IS WHEN "000"=> y <= "11111110" WHEN "001" => y <= "11111101" WHEN "010" => y <

5、= "11111011"（10） WHEN "011" => y <= "11110111" WHEN "100" => y <= "11101111" WHEN "101" => y <= "11011111" WHEN "110" => y <= "10111111" （12） WHEN "111" => y <= "011

6、11111" WHEN OTHERS=> y <= "XXXXXXXX" END CASE; ELSE y <= "11111111"（14） END IF; END PROCESS;（16）END rtl; 4、三態門電原理圖如右圖所示，真值表如左圖所示，請完成其VHDL程序構造體部分。（本題14分）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_gate ISPORT(din,en:IN STD_LOGIC; dout : OUT STD_LOGIC);END tr

7、i_gate ;ARCHITECTURE zas OF tri_gate ISBEGIN PROCESS (din,en) BEGINIF (en=1') THEN dout <= din;ELSE dout <= Z; END IF; END PROCESS ;END zas ;四、 編程題（共50分）1、根據一下四選一程序的結構體部分，完成實體程序部分（本題8分）entity MUX4 is port( (2)s:in std_logic_vector(1 downto 0); (4)d:in std_logic_vector(3 downto 0); (6)y:out

8、 std_logic (8); end MUX4; architecture behave of MUX4 isbeginprocess(s)beginif (s="00") theny<=d(0); elsif (s="01") theny<=d(1); elsif (s="10") theny<=d(2); elsif (s="11") theny<=d(3); elsenull; end if;end process;end behave; 2、編寫一個數值比較器VHDL程序的進程（不

9、必寫整個結構框架），要求使能信號g低電平時比較器開始工作，輸入信號p = q，輸出equ為0，否則為1。（本題10分）process(p,q)(2)beginif g='0' then(4)if p = q thenequ <= '0' (6)else equ <= '1' (8)end if;else equ <= '1' (10)end if;end process;3、填寫完成一個8-3線編碼器的VHDL程序（16分）。Library ieee;use ieee.std_logic_1164.all;use

10、 ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity eight_tri is port(b:in std_logic_vector(7 downto 0); （2）en:in std_logic;y:outstd_logic_vector(2 downto 0) （4）);end eight_tri;architecture a of eight_tri is （6）signal sel: std_logic_vector(8 downto 0);beginsel<=en & b; （8）y<=

11、“000” when (sel=”100000001”)else“001” when (sel=”100000010”)else （10）“010” when (sel=”100000100”)else“011” when (sel=”100001000”)else“100” when (sel=”100010000”)else （12） “101” when (sel=”100100000”)else“110” when (sel=”101000000”)else （14）“111” when (sel=”110000000”)else （16）“zzz”;end a;4、圖中給出了4位逐位

12、進位全加器，請完成其VHDL程序。（本題16分）library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity full_add isport (a,b: instd_logic_vector (3 downto 0); （2）carr: inout std_logic_vector (4 downto 0);sum: outstd_logic_vector (3 downto 0);end full_add;architecture ful

13、l_add_arch of full_add iscomponent adder （4）port (a,b,c:instd_logic;carr: inoutstd_logic;sum: out std_logic （6）);end component;begincarr(0)<='0'u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder port map(a(1),b(1),carr(1),carr(2),sum(1); （8）（10）u2:adder port map(a(2),b(2),carr(2)

14、,carr(3),sum(2); （12）u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3); （14）（16）end full_add_arch;四、 編程（共50分）1、完成下圖所示的觸發器。（本題10分）CLRCLKDQQNlibrary IEEE;use IEEE.std_logic_1164.all;entity VposDff is port (CLK, CLR, D: in STD_LOGIC; -2分 Q, QN: out STD_LOGIC ); -4分end VposDff;architecture VposDff_arch

15、 of VposDff isbegin process ( CLK, CLR ) -6分 begin if CLR='1' then Q <= '0' QN <='1' elsif CLK'event and CLK='1' then Q <= D; QN <= not D; -8分 end if; end process; -10分end VposDff_arch; 2、完成以下4位全加器代碼（本題10分）library IEEE;use IEEE.std_logic_1164.all;entit

16、y full_add isport (a,b: instd_logic_vector (3 downto 0);cin: instd_logic;cout: out std_logic;sum: outstd_logic_vector (3 downto 0);end full_add;architecture full_add_arch of full_add iscomponent adderport (a,b,c:instd_logic;carr: outstd_logic;sum: out std_logic);end component;signal c1,c2,c3: std_lo

17、gic; 2分beginu0:adder port map(a(0),b(0),cin,c1,sum(0); 4分u1:adder port map(a(1),b(1),c1,c2,sum(1); 5分u2:adder port map(a(2),b(2),c2,c3,sum(2); 6分u3:adder port map(a(3),b(3),c3,cout,sum(3); 10分end full_add_arch;3、補充完整如下代碼，使之完成4狀態不斷循環。(本題10分)ARCHITECTURE arc OF ss IStype states is ( st0,st1,st2,st3 );

18、 2分signal outc: states; 4分BEGINPROCESS(clk) BEGIN IF reset='1' then outc <=st0 ; 6分 elsif clk'event and clk='1' then CASE outc IS WHEN st0 => outc <= st1; 7分 WHEN st1 => outc <= st2; 8分 WHEN st2 => outc <= st3; 9分 WHEN st3 => outc <= st0; 10分 WHEN OTHER

19、S => outc <=st0; END CASE; end if;END PROCESS;END arc; 4、設計異或門邏輯：（本題20分）如下異或門，填寫右邊的真值表。（此項5分）ABY000011101110其表達式可以表示為：（此項5分） 這一關系圖示如下：試編寫完整的VHDL代碼實現以上邏輯。可以采用任何描述法。（此項10分）library ieee;use ieee.std_logic_1164.all; 1分entity yihuo1 isport(a,b:in std_logic;y:out std_logic);end yihuo1; 4分architectur

20、e yihuo1_behavior of yihuo1 isbegin 7分process(a,b) y<=a xor b;begin （第2種寫法）if a=b theny<='0'elsey<='1'end if;end process; end yihuo1_behavior; 10分四、 編程（共50分，除特殊聲明，實體可只寫出PORT語句，結構體要寫完整）1、用IF語句編寫一個二選一電路，要求輸入a、b, sel為選擇端，輸出q。（本題10分）Entity sel2 isPort (a,b : in std_logic;sel : i

21、n std_logic;q : out std_logic);End sel2;(3)Architecture a of sel2 isbeginif sel = 0 thenq <= a;(6)elseq <= b;(9)end if;end a;(10)2、編寫一個4位加法計數器VHDL程序的進程（不必寫整個結構框架），要求復位信號reset低電平時計數器清零，變高后，在上升沿開始工作；輸入時鐘信號為clk，輸出為q。（本題10分）Process(reset,clk)(2)beginif reset = 0 thenq <= “0000”;(4)elsif clkeven

22、t and clk = 1 then(6)q <= q + 1;(9)end if;end process;(10)3、填寫完成一個8-3線編碼器的真值表（5分），并寫出其VHDL程序（10分）。8 -3線編碼器真值表enby0y1y21000000000001000000100011000001000101000010000111000100001001001000001011010000001101100000001110xxxxxxxx高阻態entity eight_tri is port(b:in std_logic_vector(7 downto 0);en:in std_lo

23、gic;y:outstd_logic_vector(2 downto 0);end eight_tri;(3)architecture a of eight_tri is signal sel: std_logic_vector(8 downto 0);(4)beginsel<=en & b;y<= “000” when (sel=”100000001”)else“001” when (sel=”100000010”)else“010” when (sel=”100000100”)else“011” when (sel=”100001000”)else“100” when

24、(sel=”100010000”)else“101” when (sel=”100100000”)else“110” when (sel=”101000000”)else“111” when (sel=”110000000”)else(9)“zzz”;(10)end a;4、根據已給出的全加器的VHDL程序，試寫出一個4位逐位進位全加器的VHDL程序。（本題15分）library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity adder i

25、sport (a,b,c:in std_logic;carr: inout std_logic;sum: out std_logic);end adder;architecture adder_arch of adder isbeginsum <= a xor b xor c;carr <= (a and b) or (b and c) or (a and c);end adder_arch;entity full_add isport (a,b: instd_logic_vector (3 downto 0);carr: inout std_logic_vector (4 dow

26、nto 0);sum: outstd_logic_vector (3 downto 0);end full_add;(5)architecture full_add_arch of full_add iscomponent adderport (a,b,c:instd_logic;carr: inoutstd_logic;sum: out std_logic);end component;(10)begincarr(0)<='0'u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder port map(a(1

27、),b(1),carr(1),carr(2),sum(1);u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2);u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3);end full_add_arch;(15)四、 編程（共50分，除特殊聲明，實體可只寫出PORT語句，結構體要寫完整）1、用IF語句編寫一個四選一電路，要求輸入d0d3, s為選擇端，輸出y。（本題10分）entity MUX4 is port(s:in std_logic_vector(1 downto 0);d:in std_l

28、ogic_vector(3 downto 0);y:out std_logic);end MUX4; (3)architecture behave of MUX4 isbeginprocess(s)beginif (s="00") theny<=d(0); (4)elsif (s="01") theny<=d(1); (5)elsif (s="10") theny<=d(2); (6)elsif (s="11") theny<=d(3); (7)elsenull; (9)end if;end

29、 process;end behave; (10)2、編寫一個數值比較器VHDL程序的進程（不必寫整個結構框架），要求使能信號g低電平時比較器開始工作，輸入信號p = q，輸出equ為0，否則為1。（本題10分）process(p,q)(2)beginif g='0' then(4)if p = q thenequ_tmp <= '0'(6)else equ_tmp <= '1'(8)end if;else equ_tmp <= '1'(10)end if;end process;3、填寫完成一個3-8線譯碼器的

30、真值表（5分），并寫出其VHDL程序（10分）。3-8譯碼器的真值表ena2a1a0y1000000000011001000000101010000001001011000010001100000100001101001000001110010000001111100000000xxx00000000entity tri_eight is port(a:in std_logic_vector (2 downto 0);en:in std_logic;y:outstd_logic_vector (7 downto 0);end tri_eight;(2)architecture a of tri

31、_eight is signal sel:std_logic_vector (3 downto 0);(4)beginsel(0) <= a(0);sel(1) <= a(1);sel(2) <= a(2);sel(3) <= en;(5)with sel selecty <= "00000001" when "1000","00000010" when "1001","00000100" when"1010","00001000" when"1011","00010000" when"1100","00100000" when"1101","01000000" when"1110&qu