LatticeECP3設(shè)計的FPGA視頻協(xié)議開發(fā)技術(shù)本文介紹了LatticeECP3FPGA系列主要特性，LatticeECP3-35簡化方框圖以及LatticeECP3視頻協(xié)議板主要特性，方框圖和詳細的電路圖。Lattice公司的LatticeECP3FPGA系列能提供高性能的特性如增強的DSP架構(gòu)，高速SERDES和高速源同步接口。LatticeECP3系列采用65nm技術(shù)，有149K邏輯單元和支持多達486個用戶I/O，可提供多達320個18x18乘法器以及各種并行I/O標準。廣泛用于批量生產(chǎn)的對成本和功耗敏感的有線和無線基礎(chǔ)設(shè)備以及各種多媒體設(shè)備。LatticeECP3主要特性：

HigherLogicDensityforIncreasedSystemIntegration

?17Kto149KLUTs

?133to586I/Os

EmbeddedSERDES

?150Mbpsto3.2GbpsforGeneric8b10b,10-bitSERDES,and8-bitSERDESmodes

?DataRates230Mbpsto3.2Gbpsperchannelforallotherprotocols

?Upto16channelsperdevice:PCIExpress,SONET/SDH,Ethernet(1GbE,SGMII,XAUI),CPRI,SMPTE3GandSerialRapidIO

sysDSP?

?Fullycascadableslicearchitecture

?12to160slicesforhighperformancemultiplyandaccumulate

?Powerful54-bitALUoperations

?TimeDivisionMultiplexingMACSharing

?Roundingandtruncation

?Eachslicesupports

–Half36x36,two18x18orfour9x9multipliers

–Advanced18x36MACand18x18Multiply-Multiply-Accumulate(MMAC)operations

FlexibleMemoryResources

?Upto6.85MbitssysMEM?EmbeddedBlockRAM(EBR)

?36Kto303KbitsdistributedRAM

sysCLOCKAnalogPLLsandDLLs

?TwoDLLsanduptotenPLLsperdevice

Pre-EngineeredSourceSynchronousI/O

?DDRregistersinI/Ocells

?Dedicatedread/writelevellingfunctionality

?Dedicatedgearinglogic

?Sourcesynchronousstandardssupport

–ADC/DAC,7:1LVDS,XGMII

–HighSpeedADC/DACdevices

?DedicatedDDR/DDR2/DDR3memorywithDQSsupport

?OptionalInter-SymbolInterference(ISI)correctiononoutputs

ProgrammablesysI/O?BufferSupportsWideRangeofInterfaces

?On-chiptermination

?Optionalequalizationfilteroninputs

?LVTTLandLVCMOS33/25/18/15/12

?SSTL33/25/18/15I,II

?HSTL15IandHSTL18I,II

?PCIandDifferentialHSTL,SSTL

?LVDS,Bus-LVDS,LVPECL,RSDS,MLVDS

FlexibleDeviceConfiguration

?DedicatedbankforconfigurationI/Os

?SPIbootflashinterface

?Dual-bootimagessupported

?SlaveSPI

?TransFR?I/Oforsimplefieldupdates

?SoftErrorDetectembeddedmacro

SystemLevelSupport

?IEEE1149.1andIEEE1532compliant

?RevealLogicAnalyzer

?ORCAstraFPGAconfigurationutility

?On-chiposcillatorforinitialization&generaluse

?1.2Vcorepowersupply

LatticeECP3?系列選擇指引表：

圖1。LatticeECP3-35簡化方框圖（頂層）

LatticeECP3視頻協(xié)議板

LatticeECP3VideoProtocolBoard

TheLatticeECP3?FPGAfamilyincludesmanyfeaturesforvideoapplications.Forexample,DisplayPort,SMPTEstandards(SD-SDI,HD-SDIand3G-SDI),DVB-ASI,DVIandHDMIcanbeimplementedwith16channelsofembeddedSERDES/PCS.7:1LVDSvideointerfaceslikeChannelLinkandCameraLinkcanbesupportedbythegenericDDRX2modeontheI/Opins.WhenconfiguringtoTRLVDSmode,theI/Opinsonbanks0and1canalsobeusedtoreceivetheTMDSsignalsofDVIorHDMIvideostandard.

Thisuser’sguidedescribesrevisionCoftheLatticeECP3VideoProtocolBoardfeaturingtheLatticeECP3LFE3-95E-7FN1156CFPGAdevice.Thestand-aloneevaluationPCBprovidesafunctionalplatformfordevelopmentandrapidprototypingofmanydifferentvideoapplications.

圖2。LatticeECP3視頻協(xié)議板外形圖-Rev.C

主要特性：

?Videointerfacesforinterconnectiontovideostandardequipment

?AllowthedemonstrationofSD/HD/3G-SDI,DisplayPortandPCIExpress(x4)interfacesusingSERDESchannels

?HighspeedMezzanineconnectorconnectedtoSERDESchannelsforfutureexpansion

?AllowsthedemonstrationofLVDSvideostandards–ChannelLinkandCameraLink

?AllowscontrolofSERDESPCSregistersusingtheSerialClientInterface(ORCAstra)

?AllowsthedemonstrationofreceivingTMDSsignalsusingtheDVIinterface

?On-boardBootFlashwithSerialSPIFlashmemorydevice

?ShowsinteroperationwithhighperformanceDDR2memorycomponents

?Driver-based“run-time”deviceconfigurationcapabilityviaanORCAstraorRS232interface

?SMAsforexternalhigh-speedclock/PLLinputs

?Switches,LEDsandLCDdisplayheaderfordemopurposes

?MictorconnectorforusingLogicAnalyzerinthedebuggingphase

?Inputconnectionforlab-powersupply

?Powerconnectionsandpowersources

?ispVM?programmingsupport

?On-boardandexternalreferenceclocksources

?Varioushigh-speedlayoutstructures

?User-definedinputandoutputpoints

?Performancemonitoringviatestheaders,LEDsandswitches

圖3。LatticeECP3視頻協(xié)議板-Rev.C功能框圖

圖4。DisplayPort視頻接口方框圖

圖5。LatticeECP3視頻協(xié)議板方框圖

圖6。LatticeECP3視頻協(xié)議板電路圖-電源

圖7。LatticeECP3視頻協(xié)議板電路圖-電源管理

圖8。LatticeECP3視頻協(xié)議板電路圖-FPGA電源

圖9。LatticeECP3視頻協(xié)議板電路圖-FPGA配置

圖10。LatticeECP3視頻協(xié)議板電路圖-SERDES

圖11。LatticeECP3視頻協(xié)議板電路圖-DDR2存儲器

圖12。LatticeECP3視頻協(xié)議板電路圖-DVVL