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NetworkSecurityProcessorand

theRelatedSOCDesignandTestTechnologies

BistforRAmINSecondsJuly,2006NetworkSecurityProcessorandMemoryTestingProblem&SolutionsProblem:memorymanufacturingisnotperfectNeedtesting,diagnosis,andrepairRAMSES:RAM/FlashfaultsimulatorTAGS:RAM/Flashtestalgorithm(pattern)generatorBRAINS:RAMBISTgeneratorFAME:memoryfailureanalyzerDesign(Layout)DefectInjectionFaultyCellBehaviorFaultModelsFaultModelsTestAlgorithmsBuilt-InSelf-TestBuilt-InSelf-RepairTester2MemoryTestingProblem&SolutMemoryBISTAutomationFlowBRAINS:BISTforRAMsinSecondsBISTIntermediateDescriptionSimulation/Synthesis/P&RFlowBRAINSgbrainsMemoryLibraryBISTTemplatesBIDConstructorCompilerKernelBISTDesignActivationSequencesIntegrationScripts MemorySpec TestRequirementMemoryCompilerIPGeneratorsCommandScriptsGUI3MemoryBISTAutomationFlowBRATestScheduleandTestGroupingSingle-portSRAMGroup0ControllerSequencer1Dual-portSRAMGroup12R1WRegisterFileSingle-portSRAMReadportWriteportRead-writeportSequencer0Group0Parameters:MemorytypeMemoryspec.PowerconstraintUserdefine4TestScheduleandTestGroupinAlgorithmProgramming&TestScheduling5AlgorithmProgramming&TestSDrivingCapability&PipelineOptimization6DrivingCapability&PipelineBISTCircuitGenerationFlowMemoryInfo.TestAlgorithmTestSchedulingDriving/TimingSpec.BISTCompileStartRTL,TB,Syn.ScriptMemorymodel,address,wordwidthDefault/ProgrammableAuto/UserdefinedPinloading,latencyBID7BISTCircuitGenerationFlowMeBISTArchitectureMemoryBISTExternalTesterMBSMSIMBOMRDMSOMBCMBRMCKControllerRAMRAMRAMRAMRAMRAMSequencerSequencerSequencerTPGTPGTPGTPGTPGTPG8BISTArchitectureMemoryExternaExperimentResult&ComparisonMemorySpec:64X64:2modules64X128:3modules512X64:1module512X128:2modulesFullspeedtesting--clockrate:100MHzDiagnosisfunctionTestalgorithm:MarchC-(Mentor),MarchCW(BRAINS)Testtime(cycle)GatecountBRAINS2,423,50028,910Mentor20,080,90030,3539ExperimentResult&ComparisonFAMEFAME:FailureAnalyzerforMemoriesMECA:MemoryErrorCatcherandAnalyzerRAMSES:RAMfaultsimulatorTAGS:RAMtestalgorithmgeneratorERA:RAMerroranalyzerMDD:MemoryDefectDiagnosisToolAFA:AutomaticFaultAnalyzerFPA:Failure/FaultPatternAnalyzerGUI-basedFailure/FaultPatternViewer10FAMEFAME:FailureAnalyzerforFAME:FailureAnalyzerforMemory11FAME:FailureAnalyzerforMemRealisticDefectInjectionPurpose:todetermineifacircuitisdamagedbyacertaindefectOpenDefectsShortDefectsDContact/ViaMissingContactD12RealisticDefectInjectionPurpDiagnosticsUsingFaultPatternsAcause-effectapproach:FaultPatternsDefectiveNetlistRealisticFaultPatternsPredictionStageApplicationStageSimulationReductionDefectDictionaryDefectCandidates13DiagnosticsUsingFaultPatterFaultPatternAnalysisResults14FaultPatternAnalysisResultsMemoryDefectDiagnostics(MDD)MemoryDefectDiagnostics15MemoryDefectDiagnostics(MDDFailure/FaultPatternViewer16Failure/FaultPatternViewer16SummaryFault-patternorientedmethodologyfordefectdiagnosticsLayout-baseddefectinjectionanddefectdictionarycreationCombinesstrengthsofconventionalfailure-patternapproachandourfault-typeapproachIntegratedmemoryfailureanalysisframeworkCost-effectivedefectidentificationandyieldimprovementBRAINScreatesBISTcircuitforallmemorycoresUsedinearlystageofSOCdesignMemorylibraryprovideseasyaccesstodifferentmemorytypes17SummaryFault-patternorientedNetworkSecurityProcessorand

theRelatedSOCDesignandTestTechnologies

BistforRAmINSecondsJuly,2006NetworkSecurityProcessorandMemoryTestingProblem&SolutionsProblem:memorymanufacturingisnotperfectNeedtesting,diagnosis,andrepairRAMSES:RAM/FlashfaultsimulatorTAGS:RAM/Flashtestalgorithm(pattern)generatorBRAINS:RAMBISTgeneratorFAME:memoryfailureanalyzerDesign(Layout)DefectInjectionFaultyCellBehaviorFaultModelsFaultModelsTestAlgorithmsBuilt-InSelf-TestBuilt-InSelf-RepairTester19MemoryTestingProblem&SolutMemoryBISTAutomationFlowBRAINS:BISTforRAMsinSecondsBISTIntermediateDescriptionSimulation/Synthesis/P&RFlowBRAINSgbrainsMemoryLibraryBISTTemplatesBIDConstructorCompilerKernelBISTDesignActivationSequencesIntegrationScripts MemorySpec TestRequirementMemoryCompilerIPGeneratorsCommandScriptsGUI20MemoryBISTAutomationFlowBRATestScheduleandTestGroupingSingle-portSRAMGroup0ControllerSequencer1Dual-portSRAMGroup12R1WRegisterFileSingle-portSRAMReadportWriteportRead-writeportSequencer0Group0Parameters:MemorytypeMemoryspec.PowerconstraintUserdefine21TestScheduleandTestGroupinAlgorithmProgramming&TestScheduling22AlgorithmProgramming&TestSDrivingCapability&PipelineOptimization23DrivingCapability&PipelineBISTCircuitGenerationFlowMemoryInfo.TestAlgorithmTestSchedulingDriving/TimingSpec.BISTCompileStartRTL,TB,Syn.ScriptMemorymodel,address,wordwidthDefault/ProgrammableAuto/UserdefinedPinloading,latencyBID24BISTCircuitGenerationFlowMeBISTArchitectureMemoryBISTExternalTesterMBSMSIMBOMRDMSOMBCMBRMCKControllerRAMRAMRAMRAMRAMRAMSequencerSequencerSequencerTPGTPGTPGTPGTPGTPG25BISTArchitectureMemoryExternaExperimentResult&ComparisonMemorySpec:64X64:2modules64X128:3modules512X64:1module512X128:2modulesFullspeedtesting--clockrate:100MHzDiagnosisfunctionTestalgorithm:MarchC-(Mentor),MarchCW(BRAINS)Testtime(cycle)GatecountBRAINS2,423,50028,910Mentor20,080,90030,35326ExperimentResult&ComparisonFAMEFAME:FailureAnalyzerforMemoriesMECA:MemoryErrorCatcherandAnalyzerRAMSES:RAMfaultsimulatorTAGS:RAMtestalgorithmgeneratorERA:RAMerroranalyzerMDD:MemoryDefectDiagnosisToolAFA:AutomaticFaultAnalyzerFPA:Failure/FaultPatternAnalyzerGUI-basedFailure/FaultPatternViewer27FAMEFAME:FailureAnalyzerforFAME:FailureAnalyzerforMemory28FAME:FailureAnalyzerforMemRealisticDefectInjectionPurpose:todetermineifacircuitisdamagedbyacertaindefectOpenDefectsShortDefectsDContact/ViaMissingContactD29RealisticDefectInjectionPurpDiagnosticsUsingFaultPatternsAcause-effectapproach:FaultPatternsDefectiveNetlistRealisticFaultPatternsPredictionStageApplicationStageSimulationReductionDefectDictionaryDefectCandidates30

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