1、EDA課程設計題目(tm)：串口控制器設計(shj) 班級(bnj)： 姓名： 學號： 一：串口簡介(jin ji)串口是可以在使用一根線發送數據的同時用另一根線接收數據。串口通信協議也可以用于獲取遠程采集設備(shbi)的數據。通過RS232以實現計算機之間、計算機與設備之間相互(xingh)通信，目前仍是通訊領域廣泛使用的方法之一。幾乎每臺計算機都有一兩個串行接口，用來與調制解調器、實驗室設備、工控設備、POS終端等進行數據傳輸。RS-232以其方便、經濟的實現特點，一直深受工程界的青睞。不論是在電力、工控還是電信、金融交通等諸多行業都有廣泛的應用。系統主芯片采用RS-232串口通信控制器

2、，由基本時鐘發生電路模塊，復位電路模塊，波特率選擇模塊，數據幀格式選擇模塊，串并轉換模塊組成。經編譯和仿真所設計的程序，在可編程邏輯器件上下載驗證，結合FPGA技術高度靈活性與模塊化的特點，實現基本RS-232總線通信的功能，以實現串口數據幀結構選擇，串并轉換，波特率選擇等功能。通過軟件仿真，得到功能的驗證，并進行功能邏輯模塊的整合，從而驗證設計的可行性與可靠性。本模塊的功能是驗證實現和PC機進行基本的串口通信的功能。需要在PC機上安裝一個串口調試工具來驗證程序的功能。程序實現了一個收發一幀10個bit（即無奇偶校驗位）的串口控制器，10個bit是1位起始位，8個數據位，1個結束位。串口的波特

3、率由程序中定義的div_par參數決定，更改該參數可以實現相應的波特率。程序當前設定的div_par 的值是0 x104，對應的波特率是9600。用一個8倍波特率的時鐘將發送或接受每一位bit的周期時間劃分為8個時隙以使通信同步.程序的工作過程是：串口處于全雙工工作狀態，按動SW0，FPGA向PC發送“welcome字符串（串口調試工具設成按ASCII碼接受方式）；PC可隨時向FPGA發送0-F的十六進制數據，FPGA接受后顯示在7段數碼管上。二：設計方案。1:接收模塊設計串口接收模塊針對于接收串行數據進行協議包的解析，實現串行數據輸入，并行數據輸出的功能，從接收判斷的角度，實現了對于串口協議

4、的解析功能。2: 發送模塊設計串口發送模塊針對于接收并行數據進行協議的組包設計，實現并行數據輸入，串行數據輸出的功能，從發送的角度，實現了對于串口協議的組合功能。發送模塊設計與接收模塊類似，依然針對波特率，數據位，校驗位，停止位進行控制，實現全雙向的串口通信控制功能。三：電路原理圖四：軟件(run jin)流程五：實驗(shyn)源程序library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY UART IS PORT ( clk :

5、IN std_logic; rst : IN std_logic; rxd : IN std_logic; txd : OUT std_logic; en : OUT std_logic_vector(7 downto 0); seg_data : OUT std_logic_vector(7 DOWNTO 0); key_input : IN std_logic ); END UART;ARCHITECTURE arch OF UART IS - /inner reg/ SIGNAL div_reg : std_logic_vector(15 DOWNTO 0); SIGNAL div8_t

6、ras_reg : std_logic_vector(2 DOWNTO 0); SIGNAL div8_rec_reg : std_logic_vector(2 DOWNTO 0); SIGNAL state_tras : std_logic_vector(3 DOWNTO 0); SIGNAL state_rec : std_logic_vector(3 DOWNTO 0); SIGNAL clkbaud_tras : std_logic; SIGNAL clkbaud_rec : std_logic; SIGNAL clkbaud8x : std_logic; SIGNAL recstar

7、t : std_logic; SIGNAL recstart_tmp : std_logic; SIGNAL trasstart : std_logic; SIGNAL rxd_reg1 : std_logic; SIGNAL rxd_reg2 : std_logic; SIGNAL txd_reg : std_logic; SIGNAL rxd_buf : std_logic_vector(7 DOWNTO 0); SIGNAL txd_buf : std_logic_vector(7 DOWNTO 0); SIGNAL send_state : std_logic_vector(2 DOW

8、NTO 0);- SIGNAL cnt_delay : std_logic_vector(19 DOWNTO 0);- SIGNAL start_delaycnt : std_logic; SIGNAL key_entry1 : std_logic; SIGNAL key_entry2 : std_logic; -/ CONSTANT div_par : std_logic_vector(15 DOWNTO 0) := 0000000100000100; SIGNAL txd_xhdl3 : std_logic; BEGIN en =01010101 ;- txd = txd_xhdl3; t

9、xd_xhdl3 = txd_reg ; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN cnt_delay = 00000000000000000000; start_delaycnt = 0; ELSIF(clkEVENT AND clk=1)THEN IF (start_delaycnt = 1) THEN IF (cnt_delay /= 11000011010100000000) THEN cnt_delay = cnt_delay + 00000000000000000001; ELSE cnt_delay = 00000000000000

10、000000; start_delaycnt = 0; END IF; ELSE IF (NOT key_input=1) AND (cnt_delay = 00000000000000000000) THEN start_delaycnt = 1; END IF; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN key_entry1 = 0; ELSIF(clkEVENT AND clk=1)THEN IF (key_entry2 = 1) THEN key_entry1 = 0; ELSE

11、IF (cnt_delay = 11000011010100000000) THEN IF (NOT key_input = 1) THEN key_entry1 = 1; END IF; END IF; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN div_reg = 0000000000000000; ELSIF(clkEVENT AND clk=1)THEN IF (div_reg = div_par - 0000000000000001) THEN div_reg = 00000000

12、00000000; ELSE div_reg = div_reg + 0000000000000001; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN clkbaud8x = 0; ELSIF(clkEVENT AND clk=1)THEN IF (div_reg = div_par - 0000000000000001) THEN clkbaud8x = NOT clkbaud8x; END IF; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BE

13、GIN IF (NOT rst = 1) THEN div8_rec_reg = 000; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1) THEN IF (recstart = 1) THEN div8_rec_reg = div8_rec_reg + 001; END IF; END IF; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BEGIN IF (NOT rst = 1) THEN div8_tras_reg = 000; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1

14、) THEN IF (trasstart = 1) THEN div8_tras_reg = div8_tras_reg + 001;- END IF; END IF; END IF; END PROCESS; PROCESS(div8_rec_reg) BEGIN IF (div8_rec_reg = 111) THEN clkbaud_rec = 1; ELSE clkbaud_rec = 0; END IF; END PROCESS; PROCESS(div8_tras_reg) BEGIN IF (div8_tras_reg = 111) THEN clkbaud_tras = 1;

15、ELSE clkbaud_tras = 0; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BEGIN IF (NOT rst = 1) THEN txd_reg = 1; trasstart = 0; txd_buf = 00000000; state_tras = 0000; send_state = 000; key_entry2 = 0; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1) THEN IF (NOT key_entry2 = 1) THEN IF (key_entry1 = 1) THEN key

16、_entry2 = 1; txd_buf IF (NOT trasstart=1) AND (send_state 111) ) THEN trasstart = 1; ELSE IF (send_state 111) THEN IF (clkbaud_tras = 1) THEN txd_reg = 0; state_tras = state_tras + 0001; END IF; ELSE key_entry2 = 0; state_tras - IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) =

17、txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOW

18、NTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_

19、buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = txd_buf(0); txd_buf(6 DOWNTO 0) = txd_buf(7 DOWNTO 1); state_tras IF (clkbaud_tras = 1) THEN txd_reg = 1; txd_buf = 01010101; state_tras IF (clkbaud_tras = 1) THEN state_tras = state_tras + 0001; send_state = send

20、_state + 001; trasstart txd_buf txd_buf txd_buf txd_buf txd_buf txd_buf txd_buf IF (clkbaud_tras = 1) THEN state_tras = state_tras + 0001; trasstart = 1; END IF; END CASE; END IF; END IF; END IF; END PROCESS; PROCESS(clkbaud8x,rst) BEGIN IF (NOT rst = 1) THEN rxd_reg1 = 0; rxd_reg2 = 0; rxd_buf = 00

21、000000; state_rec = 0000; recstart = 0; recstart_tmp = 0; ELSE IF(clkbaud8xEVENT AND clkbaud8x = 1) THEN rxd_reg1 = rxd; rxd_reg2 = rxd_reg1; IF (state_rec = 0000) THEN IF (recstart_tmp = 1) THEN recstart = 1; recstart_tmp = 0; state_rec = state_rec + 0001; ELSE IF (NOT rxd_reg1 AND rxd_reg2) = 1) T

22、HEN recstart_tmp = 0001 AND state_rec=1000) THEN IF (clkbaud_rec = 1) THEN rxd_buf(7) = rxd_reg2; rxd_buf(6 DOWNTO 0) = rxd_buf(7 DOWNTO 1); state_rec = state_rec + 0001; END IF; ELSE IF (state_rec = 1001) THEN IF (clkbaud_rec = 1) THEN state_rec = 0000; recstart seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data seg_data = 11111111; END CASE; END PROCESS;END arch;六：總結(zngji)在此次(c c)的RS-232串口通信(tng xn)控制器設計過程中，更進一步地熟悉有關數字電路的知識和具體應用。學會了利QuarterII軟件進行原理圖的繪制，硬件描述語言VHDL的編寫，程序的仿真等工作。并能根據仿真