1、四、課程設計的總體步驟1、單個字符的顯示（如：黃）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport( clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture one of xianshi issignal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signa

2、l i:integer range 0 to 31;signal coi:std_logic;begin process(sel,clk1)begincase sel is when others =>null; end case; if clk1'event and clk1='1'then si<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if

3、;end process;sck<=clk1;end ;時序仿真：從圖中可以看出，當clk1在第32個上升沿rck變為低電頻，sck與clk1是同一電頻，故此程序滿足要求。 2、多個字符的跳動顯示（如：黃小紅）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport( clk1:in std_logic;clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture o

4、ne of xianshi issignal lie:std_logic_vector(3 downto 0);signal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signal i:integer range 0 to 31;signal coi:std_logic;begin process(sel,clk1,clk2)beginif clk2'event and clk2='1' then lie<=lie+'1' end if; cas

5、e lie is when "0000"=> case sel is when others =>null; end case; when"0001"=> case sel is when others =>null; end case; when"0010"=> case sel is when others =>null; end case; when others=>null; end case; if clk1'event and clk1='1'then si

6、<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if;end process;sck<=clk1;end ; 時序仿真：從上圖看出，當clk1在第32個上升沿rck變為低電頻，sck與clk1是同一電頻，故此程序滿足要求。3、漢字的滾動和動畫顯示（如：黃小紅+笑臉）：library ieee;use ieee.std_logic_1164.all;use ieee.std_

7、logic_unsigned.all;entity xianshi isport( clk1:in std_logic;clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture one of xianshi issignal lie:std_logic_vector(3 downto 0);signal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signal i:integer range 0 to

8、 31;signal coi:std_logic;begin process(sel,clk1,clk2)beginif clk2'event and clk2='1' then lie<=lie+'1' end if; case lie is when "0000"=> case sel is when others =>null; end case; when"0001"=> case sel is when others =>null; end case; when"0

9、010"=> case sel is when others =>null; end case; when"0011"=> case sel is when others =>null; end case; when"0100"=> case sel is when others =>null; end case; when"0101"=> case sel is when others =>null; end case; when"0110"=> c

10、ase sel is when others =>null; end case; when"0111"=> case sel is when others =>null; end case; when"1000"=> case sel is when others =>null; end case; when"1001"=> case sel is when others =>null; end case; when"1010"=> case sel is when

11、others =>null; end case; when"1011"=> case sel is when others =>null; end case; when"1100"=> case sel is when others =>null; end case; when"1101"=> case sel is when others =>null; end case; when"1110"=> case sel is when others =>null

12、; end case; when"1111"=> case sel is when others =>null; end case;when others =>null; end case; if clk1'event and clk1='1'then si<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if;end

13、process;sck<=clk1;end ；時序仿真：從上圖看出，當clk1在第32個上升沿rck變為低電頻，sck與clk1是同一電頻，si為輸出電頻，故此程序滿足要求。五、結論與收獲在三周的EDA課程設計過程中，我對VHDL語言有了更加深刻的認識。VHDL是超高速集成電路的硬件描述語言，它能夠描述硬件的結構、行為與功能。另外，VHDL具有并發性，采用自上而下的結構式設計方法，適合大型設計工程的分工合作。在編寫程序的時候，我才發現能看懂程序和能自己寫程序是兩個完全不同的概念，自己一開始寫程序時，即便是一個很簡單的功能模塊，在編譯時也可能產生很多錯誤，在不斷的改錯過程中，自己對VHDL語言的語法結構有了深刻的理解，對編譯過程中常見的錯誤也有了全面的認識。通過這十三周的課程設計，我在熟悉了基于FPGA設計的同時，也學到了很多在學習課本知識時所體會不到的東西。完成此次設計后，我不僅能對Quartus II開發仿真軟件熟練操作，能達到學以致用，同時還掌握了矩陣鍵盤和16×16點陣的工作原理。經過這一過程，我發現平常的學習在注重理論知識的掌握同時，要加強實驗環節，只有通過不斷