1、lattice ice40 hx超低功耗mobilefpga系列開發方案lattice公司的ice40 hx超低功耗mobile系列,和其它任何的或fpga器件相比,可提供最低的靜態和動態功耗,大約640到7680個規律單元和觸發器,每個器件包含8到32個ram區塊,每個區塊有4kb存儲,用于數據存儲和緩沖,特殊適合對成本敏感和量大的應用.本文介紹了ice40 hx系列主要特性,ice40 hx系列架構圖,主要產品和特性,以及iceblink40 ice40hx1k 評估板主要特性,主要元件清單和元件布局圖.the lattice semiconductor ice40 lp-series a

2、nd hx-series programmable logic family are designed to deliver the lowest static and dynamic power consumption of any comparable cpld or fpga device. ice40 fpgas are designed specifically for cost-sensitive, high-volume applications. ice40 fpga are fully user-programmable and can self-configure from

3、 a configuration image stored in on-chip, nonvolatile configuration memory (nvcm) or stored in an external commodity spi serial flash prom or downloaded from an external processor over an spi-like serial port. ice40 components deliver from approximately 640 to 7,680 logic cells and flip-flops while

4、consuming a fraction of the power of comparable programmable logic devices. each ice40 device includes 8 to 32 ram blocks, each with 4kbits storage, for on-chip data storage and data buffering.each ice40 device consists of five primary architectural elements.an array of programmable logic blocks (pl

5、bs)each plb contains eight logic cells (lcs); each logic cell consists of a fast, four-input look-up table (lut4) capable of implementing any combinational logic function of up to four inputs, regardless of complexityad-type flip-flop with an optional clock-enable and set/reset controlfast carry log

6、ic accelerates arithmetic functions: adders, subtracters, comparators, and counters.common clock input with polarity control, clock-enable input, and optional set/reset control input to the plb is shared among all eight logic cellstwo-port, 4kbit ram blocks (ram4k)256x16 default configuration; selec

7、table data width using programmable logic resourcessimultaneous read and write access; ideal for fifo memory and data buffering applicationsram contents pre-loadable during configurationfour i/o banks with independent supply voltage, multiple programmable input/output (pio) blockslv i/o standards and lvds outputs supported in all banksi/o bank 3 supports additional lvds, and sublvds i/o standardsone or two phase-locked loops (pll)very low powerclock multiplication and divisionphase shifting in fixed 90° incrementsstatic or dynamic phase shiftingprogrammable interconnections betwee