1、加減法module addsub( input 7:0 dataa,input 7:0 datab,input add_sub,/ if this is 1, add; else subtractinput clk,output reg 8:0 result );always (posedge clk)beginif (add_sub) result <= dataa + datab;/or "assign cout,sum=dataa+datab;else result <= dataa - datab;endendmodule四位的 全加法器.module add4(

2、cout,sum,a,b,cin)input3:0a,b; input cin;output 3:0 sum; output cout;assign cout,sum=a+b+cin;endmodule補碼不僅可以執行正值和負值轉換，其實補碼存在的意義，就是避免計算機去做減法的操作。1101-3 補+1000801015假設 -3 + 8 ，只要將-3 轉為補碼形式，亦即0011 => 1101 ，然后和8，亦即 1000 相加就會得到5，亦即 0101 。至于溢出的最高位可以無視掉。乘法器module mult(outcome,a,b);parameter SIZE=8;inputSI

3、ZE:1 a,b;output reg2*SIZE:1 outcome;integer i;always (a or b)begin outcome<=0;for(i=0,i<=SIZE;i=i+1)if(bi) outcome<=outcome+(a<<(i-1); endendmodule另一種乘法器。在初始化之際，取乘數和被乘數的正負關系，然后取被乘數和乘數的正值。輸出結果根據正負關系取得。else if( Start_Sig )case( i )0:beginisNeg <= Multiplicand人 Multiplier7;Mcand <=

4、 Multiplicand7 ? ( Multiplicand + 1'b1 ) : Multiplicand;Mer <= Multiplier7 ? ( Multiplier + 1'b1 ) : Multiplier;Temp <= 16'd0;i <= i + 1'b1; end1: / Multiplingif( Mer = 0 ) i <= i + 1'b1;else begin Temp <= T emp + Mcand; Mer <= Mer - 1'b1; end2: begin isDone

5、 <= 1'b1; i <= i + 1'b1; end3: begin isDone <= 1'b0; i <= 2'd0; endendcaseassign Done_Sig = isDone;assign Product = isNeg ? ( Temp + 1'b1 ) : Temp;endmodulebooth 乘法器module booth_multiplier_module(input CLK,input RSTn,input Start_Sig,input 7:0A,input 7:0B,output Done_S

6、ig,output 15:0Product,output 7:0SQ_a,output 7:0SQ_s,output 16:0SQ_p);reg 3:0i;reg 7:0a;/ result of Areg 7:0s;/ reverse result of Areg 16:0p;/ p 空間， 16+1 位reg 3:0X;/指示 n 次循環reg isDone;always ( posedge CLK or negedge RSTn )if( !RSTn )begini <= 4'd0;a <= 8'd0;s <= 8'd0; p <= 17&

7、#39;d0;X <= 4'd0;isDone <= 1'b0;endelse if( Start_Sig )case( i )0:begin a <= A; s <= ( A + 1'b1 ); p <= 8'd0 , B , 1'b0 ; i <= i + 1'b1; end1:if( X = 8 ) begin X <= 4'd0; i <= i + 4'd2; endelse if( p1:0 = 2'b01 ) begin p <= p16:9 + a , p

8、8:0 ; i <= i + 1'b1; endelse if( p1:0 = 2'b10 ) begin p <= p16:9 + s , p8:0 ; i <= i + 1'b1; endelse i <= i + 1'b1;/00 和 11 ，無操作2:begin p <= p16 , p16:1 ; X <= X + 1'b1; i <= i - 1'b1; end/ 右移，最高位補0 or 1.3:begin isDone <= 1'b1; i <= i + 1'b1

9、; end4:begin isDone <= 1'b0; i <= 4'd0; endendcaseassign Done_Sig = isDone;assign Product = p16:1;endmodule除法器module divider_module(input CLK,input RSTn,input Start_Sig,input 7:0Dividend,input 7:0Divisor,output Done_Sig,output 7:0Quotient,output 7:0Reminder,);reg 3:0i;reg 7:0Dend;reg 7

10、:0Dsor;reg 7:0Q;reg 7:0R;reg isNeg;reg isDone;always ( posedge CLK or negedge RSTn )if( !RSTn )begini <= 4'd0;Dend <= 8'd0;Dsor <= 8'd0;Q <= 8'd0;isNeg <= 1'b0;isDone <= 1'b0;endelse if( Start_Sig )case( i )0:beginDend <= Dividend7 ? Dividend + 1'b1 :

11、 Dividend;Dsor <= Divisor7 ? Divisor : ( Divisor + 1'b1 );isNeg <= Dividend7 A Divisor7;i <= i + 1'b1;end1: if( Divisor > Dend )begin Q <= isNeg ? ( Q + 1'b1 ) : Q; i <= i + 1'b1; endelse begin Dend <= Dend + Dsor; Q <= Q + 1'b1; end2: begin isDone <= 1

12、'b1; i <= i + 1'b1; end3: begin isDone <= 1'b0; i <= 4'd0; end endcaseassign Done_Sig = isDone;assign Quotient = Q;assign Reminder = Dend;endmodule除法器 2module div(a,b,clk,result,yu)input3:0a,b;output reg3:0 result,yu;input clk; reg1:0 state;reg3:0 m,n;parameter S0=2'b00,

13、S1=2'b01,S2=2'b10;always(posedge clk)begin case(state)S0: begin if(a>b) begin n<=a-b;m<=4'b0001; state<=S1; end else begin m<=4'b0000;n<=a; state<=S2; endend51: begin if(n>=b) begin m<=m+1;n<=n-b;state<=S1;end else begin state<=S2;endend52: begin r

14、esult<=m;yu<=n;state<=S0;enddefule:state<=S0;endcaseendendmodule13 、一個可預置初值的7 進制循環計數器 verilogmodule count(clk,reset,load,date,out);input load,clk,reset;input3:0 date;output reg3:0 out;parameter WIDTH=4'd7;always(clk or reset)beginif(reset) out<=4'd0;else if(load) out<=date;

15、else if(out=WIDTH-1) out<=4'd0;elseout<=out+1;endendmoduleJohnson 計數器約翰遜 (Johnson) 計數器又稱扭環計數器,是一種用n 位觸發器來表示2n 個狀態的計數器。它與環形計數器不同，后者用n位觸發器僅可表示n個狀態。n位二進制計數器(n為觸發器的個數)有2小 個狀態。若以四位二進制計數器為例,它可表示16 個狀態。“ 0000-1000-1100-1110-1111-0111-0011-0001-0000-1000”module Johnson(input clk,input clr,output r

16、egN-1:0 q);always(posedge clk or negedge clr)if(!clr)q<=N1 b0else if(!q0)q<=1 b1,qN -1:1;elseq<=1 b0,qN -1:1;endmodule任意分頻，占空比不為50%always(clk)begin if(count=x-1) count<=0;else count<=count+1; endassign clkout=county/y 一般用 count 的最高位偶數分頻(8 分頻，占空比50%) (計數至n-1 ，翻轉)module count5(reset,clk

17、,out)input clk,reset; output out;reg1:0 count;always(clk)if(reset) begin count<=0; out<=0; endelse if(count=3) begin count<=0;out<=!out: endelse count<=count+1;endmodule奇數分頻電路(占空比50% ) 。module count5(reset,clk,out)input clk,reset;output out;reg2:0 m,n;reg count1;reg count2; always(pos

18、edge clk) begin/ “4”為分頻數NUM-1end,NUM=5if(reset) begin m<=0;count1<=0;endelse begin if(m=4) m<=0; else m<=m+1;if(m<2) count1<=1; else count1<=0; end always(negedge clk)beginif(reset) begin n<=0;count2<=0;endelse begin if(n=4) n<=0; else n<=n+1;if(n<2) count2<=1;

19、 else count2<=0;endend assign out=count1|count2;半整數分頻module fdiv5_5(clkin,clr,clkout)input clkin,clr; output reg clkout;reg clk1; wire clk2; integer count;xor xor1(clk2,clkin,clk1)always(posedge clkout or negedge clr)begin if(clr) begin clk1<=1' b0; endelse clk1<=clk1;endalways( posedge

20、 clk2 or negedge clr)begin if(clr)begin count<=0; clkout <=1 ' b0; endelse if(count=5)begin count<=0; clkout<=1 ' b1; endelse begin count<=count+1; clkout<=1' b0; endendendmodule小數分頻N=M/P . N為分配比，M為分頻器輸入脈沖數，P為分頻器輸出脈沖數N=(8 X9+9 X1)/ (9+1 ) =8.1 先做9次8分頻再做1次9分頻。module fdiv

21、8_1(clkin,rst,clkout)input clkin,rst; output reg clkout;reg3:0 cnt1,cnt2;always(posedge clkin or posedge rst)begin if(rst) begin cnt1<=0;cnt2<=0;clkout<=0; endelse if(cnt1<9)/cnt1,08beginif(cnt2<7) begin cnt2<=cnt2+1;clkout<=0; endelse begin cnt2<=0;cnt1<=cnt1+1;clkout<

22、=1; end endelse begin/cnt1,9if(cnt2<8) begin cnt2<=cnt2+1;clkout<=0; endelsebegin cnt2<=0;cnt1<=0;clkout<=1;endendendendmodule串并轉換module p2s(clk,clr,load,pi,so)input clk,clr,load;input 3:0 pi;output so;reg3:0 r;always(posedge clk or negedge clr)if(clr) r<=4'h0;else if(load)

23、r<=pi;else r<=r, 1'b0;/ or r<<1;assign so=r3;endmodulemodule s2p(clk,clr,en,si,po)input clk,clr,en,si;output3:0 po;always(posedge clk or negedge clr)if(clr)r<= 8 ho;elser<=r,si;assign po=(en) ? r : 4 h0;endmoduleb) 試用 VHDL 或 VERILOG 、 ABLE 描述 8 位 D 觸發器邏輯。module dff(q,qn,d,clk,s

24、et,reset)input7:0 d,set;input clk,reset;output reg7:0 q,qn;always (posedge clk)beginendif(reset) begin q<=8' h00; qn<=8' hFF; endelse if(set) begin q<=8 ' hFF; qn<=8 ' h00; else begin q<=d; qn<=d; end endendmodule序列檢測“ 101 ”module xulie101(clk,clr,x,z);input clk,clr

25、,x;output reg z;reg1:0 state,next_state;parameter S0=2'b00,s1=2'b01,s2=2'b11,s3=2'b10;always (posedge clk or posedge clr)begin if(clr) state<=s0;else state<=next_state;endalways (state or x)begincase(state)s0:begin if(x)next_state<=s1;elsenext_state<=s0;ends1:begin if(x)n

26、ext_state<=s1;elsenext_state<=s2;ends2:begin if(x)next_state<=s3;elsenext_state<=s0;ends3:begin if(x)next_state<=s1;elsenext_state<=s2;enddefault: next_state<=s0;endcaseendalways (state)begin case(state)s3:z=1;default:z=0;endcaseendendmodule按鍵消抖1 .采用一個頻率較低的時鐘，對輸入進行采樣，消除抖動。module

27、 switch(clk,keyin,keyout)parameter COUNTWIDTH=8;input clk,keyin; output reg keyout; regCOUNTWIDTH -1:0 counter;wire clk_use;/頻率較低的時鐘assign clk_use=counterCOUNTWIDTH -1;always(posegde clk)counter<=counter+1 b1;always(posedge clk_use)keyout<=keyin;endmodule2. module switch(clk,keyin,keyout)param

28、eter COUNTWIDTH=8;input clk,keyin; output reg keyout; regCOUNTWIDTH -1:0 counter;initial counter<=0,keyout<=0,keyin<=0;always(posegde clk)if(keyin=1) begin key_m<=keyin, counter<=counter+1;endelse counter<=0;if(keyin&&counterm) keyout<=1; /m 定義時延endmodule數碼管顯示module numb

29、er_mod_module/ 分別取得數字的十位和個位(CLK, RSTn, Number_Data, Ten_Data, One_Data);input CLK;input RSTn;input 7:0Number_Data;output 3:0Ten_Data;output 3:0One_Data;reg 31:0rTen;reg 31:0rOne;always ( posedge CLK or negedge RSTn )if( !RSTn )beginrTen <= 32'd0;rOne <= 32'd0;endelsebeginrTen <= Num

30、ber_Data / 10;rOne <= Number_Data % 10;endassign Ten_Data = rTen3:0;assign One_Data = rOne3:0;endmodulemodule led(CLK, Ten_Data, One_Data,led0, led1);/ 數碼管顯示input 3:0 Ten_Data, One_Data;input CLK;output 7:0 led0, led1;reg 7:0 led0, led1;always ( posedge cp_50)begincasez (One_Data)4'd0 : led0

31、= 8'b1100_0000;4'd1 : led0 = 8'b1111_1001;4'd2 : led0 = 8'b1010_0100;4'd3 : led0 = 8'b1011_0000;4'd4 : led0 = 8'b1001_1001;4'd5 : led0 = 8'b1001_0010;4'd6 : led0 = 8'b1000_0010;4'd7 : led0 = 8'b1111_1000;4'd8 : led0 = 8'b1000_0000;4

32、'd9 : led0 = 8'b1001_0000;default:led0 = 8'b1111_1111;endcasecasez (Ten_Data)4'd0 : led1 = 8'b1100_0000;4'd1 : led1 = 8'b1111_1001;4'd2 : led1 = 8'b1010_0100;4'd3 : led1 = 8'b1011_0000;4'd4 : led1 = 8'b1001_1001;4'd5 : led1 = 8'b1001_0010;4

33、'd6 : led1 = 8'b1000_0010;4'd7 : led1 = 8'b1111_1000;4'd8 : led1 = 8'b1000_0000;4'd9 : led1 = 8'b1001_0000;default:led0 = 8'b1111_1111;endcaseendendmodule5. fifo 控制器 .FIFO 存儲器 FIFO 是英文 First In First Out 的縮寫，是一種先進先出的數據緩存器，他與普通存儲器的區別是沒有外部讀寫地址線，這樣使用起來非常簡單，但缺點就是只能順序寫

34、入數據，順序的讀出數據，其數據地址由內部讀寫指針自動加1 完成，不能像普通存儲器那樣可以由地址線決定讀取或寫入某個指定的地址。在系統設計中，以增加數據傳輸率、處理大量數據流、匹配具有不同傳輸率的系統為目的而廣泛使用FIFO 存儲器，從而提高了系統性能.FIFO 參數：FIFO 的寬度，the width ，指 FIFO 一次讀寫操作的數據位；FIFO 深度， THE DEEPTH ，指 FIFO 可以存儲多少個N 位的數據；FIFO 的血操作繼續向FIFO 中寫數據而造成溢出滿標志，FIFO 已滿或將要滿時送出的一個信號，以阻止( overflow ) ；空標志，阻止FIFIO 的讀操作；mo

35、dule fifo_module (input CLK,input RSTn,input Write_Req,input 7:0FIFO_Write_Data,input Read_Req,output 7:0FIFO_Read_Data,output Full_Sig,output Empty_Sig,/*/output 7:0SQ_rS1,output 7:0SQ_rS2,output 7:0SQ_rS3,output 7:0SQ_rS4,output 2:0SQ_Count/*/ );/*/parameter DEEP = 3'd4;/*/reg 7:0rShift DEEP:0

36、;reg 2:0Count;reg 7:0Data;always ( posedge CLK or negedge RSTn )if( !RSTn )beginrShift0 <= 8'd0; rShift1 <= 8'd0; rShift2 <= 8'd0;rShift3 <= 8'd0; rShift4 <= 8'd0;Count <= 3'd0;Data <= 8'd0;endelse if( Read_Req && Write_Req && Count &l

37、t; DEEP && Count > 0 ) beginrShift1 <= FIFO_Write_Data;rShift2 <= rShift1;rShift3 <= rShift2;rShift4 <= rShift3;Data <= rShift Count ;endelse if( Write_Req && Count < DEEP ) beginrShift1 <= FIFO_Write_Data;rShift2 <= rShift1;rShift3 <= rShift2;rShift4 &l

38、t;= rShift3;Count <= Count + 1'b1;endelse if( Read_Req && Count > 0 )beginData <= rShiftCount;Count <= Count - 1'b1;end/*/assign FIFO_Read_Data = Data;assign Full_Sig = ( Count = DEEP ) ? 1'b1 : 1'b0;assign Empty_Sig = ( Count = 0 ) ? 1'b1 : 1'b0;/*/assign

39、 SQ_rS1 = rShift1;assign SQ_rS2 = rShift2;assign SQ_rS3 = rShift3;assign SQ_rS4 = rShift4;assign SQ_Count = Count;/*/Endmodulefifi 2(指針控制)module FIFO(date,q,clr,clk,we,re,ff,ef);parameter WIDTH=8,DEEPTH=8,ADDR=3;input clk,clr;input we,re;inputWIDTH-1:0 date;output ff,ef;output regWIDTH-1:0 q;regWIDT

40、H-1:0 mem_dateDEEPTH-1:0;regADDR-1:0 waddr,raddr; reg ff,ef;always(posedge clk or negedge clr)/ 寫地址begin if(!clr) waddr=0;else if(we=1&&ff=0) waddr=waddr+1;else if(we=1&&ff=0&&waddr=7) waddr=0;endalways(posedge clk)begin if(we&&!ff) mem_datewaddr=date;end/ 讀地址always(p

41、osedge clk or negedge clr) begin if(!clr) raddr=0;else if(re=1&&ef=0) raddr=waddr+1;else if(re=1&&ef=0&&raddr=7) raddr=0;endalways(posedge clk)begin if(re&&!ef) q=mem_dateraddr; endalways(posedge clk or negedge clr)begin if(!clr) ff=1'b0;else if(we & !re) && (waddr=raddr-1) | (waddr=DEEPTH-1) && (raddr=1'b0) ff=1'b1;else ff=1'b0;endalways(posedge clk or negedge clr)begin if(!clr) ef=1'b0;else if(!we & re)&&(waddr=raddr+1)|(raddr=DEEPTH-1)&&(waddr=1'b0) ef=1'b1;else ef=1'b0;