第五章VHDL基本描述語句5.1基本邏輯門電路5.2選擇器電路5.3編碼器與譯碼器電路5.4三態(tài)門及總線緩沖器電路5.5加法器電路5.6求補器電路5.7乘法器電路5.8數值比較器電路5.9移位器電路第五章VHDL基本描述語句5.1基本邏輯門電路5.1基本邏輯門電路基本門電路用VHDL語言來描述十分方便。為方便起見，在下面的兩輸入模塊中，使用VHDL中定義的邏輯運算符，同時實現一個與門、或門、與非門、或非門、異或門及反相器的邏輯。這些基本邏輯門電路都組織成基本元件的形式，編程時可直接調用。5.1基本邏輯門電路基本門電路用VHDL語言來描述十分方便5.1.12輸入與非門電路LIBRARYIEEE;--2輸入與非門USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand2;ARCHITECTUREbehavioralOFcynand2ISBEGINdataout<=datain1NANDdatain2;--行為描述ENDARCHITECTUREbehavioral;5.1.12輸入與非門電路LIBRARYIEEE;LIBRARYIEEE;--2輸入與非門USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand2;LIBRARYIEEE;--2輸入與非門ARCHITECTUREbehavioral_2OFcynand2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN“00”=>dataout<=‘1’;--結構描述

WHEN"01"=>dataout<='1';WHEN"10"=>dataout<='1';WHEN"11"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.22輸入或非門LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynor2;ARCHITECTUREbehavioralOFcynor2ISBEGINdataout<=datain1NORdatain2;ENDARCHITECTUREbehavioral;5.1.22輸入或非門LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynor2;LIBRARYIEEE;ARCHITECTUREbehavioral_2OFcynor2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN"00"=>dataout<='1';WHEN"01"=>dataout<='0';WHEN"10"=>dataout<='0';WHEN"11"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.3反相器電路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynotISPORT(datain:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynot;ARCHITECTUREbehavioralOFcynotISBEGINdataout<=NOTdatain;ENDARCHITECTUREbehavioral;5.1.3反相器電路LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynotISPORT(a,datain:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynot;ARCHITECTUREbehavioral_2OFcynotISBEGINPROCESS(a,datain)--RTL描述方式,MAX中需要加入時鐘aBEGINIF(datain='1')THENdataout<='0';ELSEdataout<='1';ENDIF;ENDPROCESS;ENDARCHITECTUREbehavioral_2;LIBRARYIEEE;仿真波形仿真波形5.1.42輸入異或門電路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyxor2;ARCHITECTUREbehavioralOFcyxor2ISBEGINdataout<=datain1XORdatain2;ENDARCHITECTUREbehavioral;5.1.42輸入異或門電路LIBRARYIEELIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyxor2;LIBRARYIEEE;ARCHITECTUREbehavioral_2OFcyxor2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN"00"=>dataout<='0';WHEN"01"=>dataout<='1';WHEN"10"=>dataout<='1';WHEN"11"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.52輸入同或門電路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynxor2;ARCHITECTUREbehavioralOFcynxor2ISBEGINdataout<=NOT(datain1XORdatain2);ENDARCHITECTUREbehavioral;5.1.52輸入同或門電路LIBRARYIEEELIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynxor2ISPORT(datain1,datain2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynxor2;LIBRARYIEEE;ARCHITECTUREbehavioral_2OFcynxor2ISBEGINPROCESS(datain1,datain2)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=datain1&datain2;CASEcombISWHEN"00"=>dataout<='1';WHEN"01"=>dataout<='0';WHEN"10"=>dataout<='0';WHEN"11"=>dataout<='1';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;ARCHITECTUREbehavioral_2OF仿真波形仿真波形5.1.6多輸入門電路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyor3ISPORT(datain1,datain2,datain3:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyor3;ARCHITECTUREbehavioralOFcyor3ISBEGINdataout<=datain1ORdatain2ORdatain3;ENDARCHITECTUREbehavioral;5.1.6多輸入門電路LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcyor3ISPORT(datain1,datain2,datain3:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcyor3;ARCHITECTUREbehavioral_2OFcyor3ISBEGINPROCESS(datain1,datain2,datain3)LIBRARYIEEE;VARIABLEcomb:STD_LOGIC_VECTOR(2DOWNTO0);BEGINcomb:=datain1&datain2&datain3;CASEcombISWHEN"000"=>dataout<='0';WHEN"001"=>dataout<='1';WHEN"010"=>dataout<='1';WHEN"011"=>dataout<='1';WHEN"100"=>dataout<='1';WHEN"101"=>dataout<='1';WHEN"110"=>dataout<='1';WHEN"111”=>dataout<='1';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;VARIABLEcomb:STD_LOGIC_VEC2.4輸入與非門電路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand4ISPORT(datain1,datain2:INSTD_LOGIC;datain3,datain4:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand4;ARCHITECTUREbehavioralOFcynand4ISBEGINdataout<=NOT(datain1ANDdatain2ANDdatain3ANDdatain4);ENDARCHITECTUREbehavioral;2.4輸入與非門電路LIBRARYIEEE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcynand4ISPORT(datain1,datain2:INSTD_LOGIC;datain3,datain4:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcynand4;ARCHITECTUREbehavioral_2OFcynand4ISBEGINPROCESS(datain1,datain2,datain3,datain4)VARIABLEcomb:STD_LOGIC_VECTOR(3DOWNTO0);BEGINcomb:=datain1&datain2&datain3&datain4;

LIBRARYIEEE;CASEcombISWHEN"0000"=>dataout<='1';WHEN"0001"=>dataout<='1';WHEN"0010"=>dataout<='1';WHEN"0011"=>dataout<='1';WHEN"0100"=>dataout<='1';WHEN"0101"=>dataout<='1';WHEN"0110"=>dataout<='1';WHEN"0111"=>dataout<='1';WHEN"1000"=>dataout<='1';WHEN"1001"=>dataout<='1';WHEN"1010"=>dataout<='1';

WHEN"1011"=>dataout<='1';WHEN"1100"=>dataout<='1';WHEN"1101"=>dataout<='1';WHEN"1110"=>dataout<='1';WHEN"1111"=>dataout<='0';WHENOTHERS=>dataout<='X';ENDCASE;ENDPROCESS;ENDARCHITECTUREbehavioral_2;CASEcombISWHEN"1011"=>5.2數據選擇器5.2數據選擇器第五章-組合邏輯電路的VHDL語言描述課件LIBRARYIEEE;--2選1數據選擇器USEIEEE.STD_LOGIC_1164.ALL;ENTITYcy2_1muxIS PORT(datain1,datain2:INSTD_LOGIC;sel:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcy2_1mux;

LIBRARYIEEE;--2選1數據選擇器ARCHITECTURErtlOFcy2_1muxISBEGINcy21mux_inst:PROCESS(datain1,datain2,sel)BEGINIF(sel='1')THEN dataout<=datain1;ELSEdataout<=datain2;ENDIF;ENDPROCESScy21mux_inst;ENDARCHITECTURErtl;ARCHITECTURErtlOFcy2_1muLIBRARYIEEE;--2選1數據選擇器USEIEEE.STD_LOGIC_1164.ALL;ENTITYcy2_1muxIS PORT(datain1,datain2:INSTD_LOGIC;sel:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYcy2_1mux;LIBRARYIEEE;--2選1數據選擇器ARCHITECTURErtlOFcy2_1muxISBEGINcy21mux_inst:PROCESS(datain1,datain2,sel)BEGINCASEselIS--CASE語句的控制表達式是selWHEN'0'=>dataout<=datain2;WHEN'1'=>dataout<=datain1;WHENOTHERS=>dataout<='0';ENDCASE;ENDPROCESScy21mux_inst;ENDARCHITECTURErtl;ARCHITECTURErtlOFcy2_1mu仿真波形仿真波形5.2.216選1選擇器5.2.216選1選擇器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcy16_1muxISPORT(gn:INSTD_LOGIC;datain:INSTD_LOGIC_VECTOR(15DOWNTO0);sel:INSTD_LOGIC_VECTOR(3DOWNTO0);dataout:OUTSTD_LOGIC);ENDENTITYcy16_1mux;

LIBRARYIEEE;ARCHITECTURErtlOFcy16_1muxISBEGINc161mux_inst:PROCESS(gn,datain,sel)

BEGINIF(gn='0')THENIF(sel="0000")THENdataout<=datain(0);ELSIF(sel="0001")THENdataout<=datain(1);ELSIF(sel="0010")THENdataout<=datain(2);ELSIF(sel="0011")THENdataout<=datain(3);ELSIF(sel="0100")THENdataout<=datain(4);

ELSIF(sel="0101")THENdataout<=datain(5);

ELSIF(sel="0110")THENdataout<=datain(6);ELSIF(sel="0111")THENdataout<=datain(7);ELSIF(sel="1000")THENdataout<=datain(8);ELSIF(sel="1001")THENdataout<=datain(9);ELSIF(sel="1010")THENdataout<=datain(10);ELSIF(sel="1011")THENdataout<=datain(11);ELSIF(sel="1100")THENdataout<=datain(12);ELSIF(sel="1101")THENdataout<=datain(13);ELSIF(sel="1110")THENdataout<=datain(14);ELSEdataout<=datain(15);ENDIF;ELSEdataout<='0';ENDIF;ENDPROCESSc161mux_inst;ENDARCHITECTURErtl;ARCHITECTURErtlOFcy16_1m5.3編碼器與譯碼器電路5.3.1編碼器5.3編碼器與譯碼器電路5.3.1編碼器8線-3線普通編碼器8線-3線普通編碼器--8線-3線普通編碼器libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;entityptbm8_3isport(a:inSTD_LOGIC_VECTOR(7downto0); y:outSTD_LOGIC_VECTOR(2downto0));endptbm8_3;--8線-3線普通編碼器architectureARCHofptbm8_3isBEGINPROCESS(a)BEGIN CASEaISwhen"00000001"=> Y<="000"; when"00000010“=> Y<="001"; when"00000100"=> Y<="010";when"00001000"=> Y<="011";when"00010000"=> Y<="100";when"00100000"=> Y<="101";when"01000000“=> Y<="110";whenothers=>Y<="111"; ENDCASE;ENDPROCESS;endARCH;architectureARCHofptbm8_3i仿真波形仿真波形第五章-組合邏輯電路的VHDL語言描述課件10線-4線優(yōu)先級編碼器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcypriority_encoderIS PORT( datain:INSTD_LOGIC_VECTOR(0TO9);dataout:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYcypriority_encoder;

ARCHITECTURErtlOFcypriority_encoderISBEGINPROCESS(datain)10線-4線優(yōu)先級編碼器LIBRARYIEEE;BEGIN IF(datain="1111111111")THEN dataout<="1111"; ELSE IF(datain(9)='0')THEN dataout<="0110"; ELSIF(datain(8)='0')THEN dataout<="0111"; ELSIF(datain(7)='0')THENdataout<="1000"; ELSIF(datain(6)='0')THENdataout<="1001"; ELSIF(datain(5)='0')THEN dataout<="1010";

ELSIF(datain(4)='0')THENdataout<="1011";ELSIF(datain(3)='0')THENdataout<="1100"ELSIF(datain(2)='0')THENdataout<="1101";ELSIF(datain(1)='0')THENdataout<="1110";ELSEdataout<="1111";ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTURErtl;BEGINELSIF(datain(4)='0'LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcypriority_encoderIS PORT( datain:INSTD_LOGIC_VECTOR(0TO9);dataout:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYcypriority_encoder;

ARCHITECTURErtlOFcypriority_encoderISBEGINPROCESS(datain)BEGIN IF(datain="1111111111")THEN dataout<="1111"; ELSE IF(datain(9)='0')THEN dataout<="0110"; ELSIF(datain(8)='0')THEN dataout<="0111"; ELSIF(datain(7)='0')THENdataout<="1000"; ELSIF(datain(6)='0')THENdataout<="1001"; ELSIF(datain(5)='0')THEN dataout<="1010";ELSIF(datain(4)='0')THENdataout<="1011";ELSIF(datain(3)='0')THENdataout<="1100";ELSIF(datain(2)='0')THENdataout<="1101";ELSIF(datain(1)='0')THENdataout<="1110";ELSEdataout<="1111";ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTURErtl;LIBRARYIEEE;8線-3線優(yōu)先編碼器8線-3線優(yōu)先編碼器8線-3線優(yōu)先編碼器LIBRARYieee;USEieee.std_logic_1164.ALL;Entitypriorityisport(A:inbit_vector(7downto0);Y:outbit_vector(2downto0));EndEntitypriority;8線-3線優(yōu)先編碼器LIBRARYieee;architecturev1ofpriorityisbeginprocess(I)beginifA(7)='1‘thenY<="111";elsifA(6)='1'thenY<="110";elsifA(5)='1'thenY<="101";elsifA(4)='1'thenY<="100";elsifA(3)='1'thenY<="011";elsifA(2)='1'thenY<="010";elsifA(1)='1'thenY<="001";elsifA(0)='1'thenY<="000";elseY<=“000”;endif;endprocess;endv1;architecturev1ofpriorityis仿真波形仿真波形5.3.2譯碼器5.3.2譯碼器4線16線譯碼器真值表4線16線譯碼器真值表LIBRARYIEEE;--4線16線譯碼器USEIEEE.STD_LOGIC_1164.ALL;ENTITYcydecoder_4_16ISPORT(D,C,B,A:INSTD_LOGIC;G1N,G2N:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(15DOWNTO0));ENDENTITYcydecoder_4_16;

ARCHITECTURErtlOFcydecoder_4_16ISSIGNALtemp_datain:STD_LOGIC_VECTOR(3DOWNTO0);BEGINtemp_datain<=D&C&B&A; PROCESS(D,C,B,A,G1N,G2N) BEGINLIBRARYIEEE;--4線16線譯碼器IF(G1N='0'ANDG2N='0')THEN--譯碼器的選通信號低電平有效

CASEtemp_datainIS WHEN"0000"=>q<="1111111111111110"; WHEN"0001"=>q<="1111111111111101"; WHEN"0010"=>q<="1111111111111011"; WHEN"0011"=>q<="1111111111110111"; WHEN"0100"=>q<="1111111111101111"; WHEN"0101"=>q<="1111111111011111"; WHEN"0110"=>q<="1111111110111111"; WHEN"0111"=>q<="1111111101111111";

IF(G1N='0'ANDG2N='0')T

WHEN"1000"=>q<="1111111011111111"; WHEN"1001"=>q<="1111110111111111"; WHEN"1010"=>q<="1111101111111111"; WHEN"1011"=>q<="1111011111111111"; WHEN"1100"=>q<="1110111111111111"; WHEN"1101"=>q<="1101111111111111"; WHEN"1110"=>q<="1011111111111111"; WHEN"1111"=>q<="0111111111111111"; WHENOTHERS=>q<="XXXXXXXXXXXXXXXX"; ENDCASE; ELSE q<="1111111111111111"; ENDIF;ENDPROCESS;ENDARCHITECTURErtl;WHEN"1000"=>仿真波形仿真波形4線10線譯碼器真值表4線10線譯碼器真值表LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcybcddecoder_4_10ISPORT(D,C,B,A:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(0TO9));ENDENTITYcybcddecoder_4_10;

ARCHITECTURErtlOFcybcddecoder_4_10ISSIGNALtemp_datain:STD_LOGIC_VECTOR(3DOWNTO0);BEGINtemp_datain<=D&C&B&A;PROCESS(temp_datain)BEGINLIBRARYIEEE;USEIEEE.STD_CASEtemp_datainIS--CASE語句的條件表達式是位矢量temp_datainWHEN"0000"=>q<="1111111110";WHEN"0001"=>q<="1111111101";WHEN"0010"=>q<=""1111111011";WHEN"0011"=>q<="1111110111";WHEN"0100"=>q<="1111101111";WHEN"0101"=>q<="1111011111";WHEN"0110"=>q<="1110111111";WHEN"0111"=>q<="1101111111";WHEN"1000"=>q<="1011111111";WHEN"1001"=>q<="0111111111";WHENOTHERS=>q<="1111111111";ENDCASE;ENDPROCESS;ENDARCHITECTURErtl;CASEtemp_datainIS--CASE仿真波形仿真波形5.4三態(tài)門及總線緩沖電路5.4.1三態(tài)門5.4三態(tài)門及總線緩沖電路5.4.1三態(tài)門LIBRARYIEEE;--用進程里的IF語句來實現USEIEEE.STD_LOGIC_1164.ALL;ENTITYtriple_bufferISPORT(datain,en:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYtriple_buffer;LIBRARYIEEE;--用進程里的IFARCHITECTUREtri_method1OFtriple_bufferISBEGINPROCESS(datain,en)BEGINIF(en='1')THENdataout<=datain;ELSEdataout<='Z';ENDIF;ENDPROCESS;ENDARCHITECTUREtri_method1;ARCHITECTUREtri_method1OF仿真波形仿真波形LIBRARYIEEE;--第三種方法用進程里的CASE語句來實現USEIEEE.STD_LOGIC_1164.ALL;ENTITYtriple_bufferISPORT(datain,en:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDENTITYtriple_buffer;LIBRARYIEEE;--第三種方法用進程里的CAARCHITECTUREtri_method3OFtriple_bufferISBEGINPROCESS(datain,en)BEGINCASEenISWHEN'1'=>dataout<=datain;WHENOTHERS=>dataout<='Z';ENDCASE;ENDPROCESS;ENDARCHITECTUREtri_method3;ARCHITECTUREtri_method3OF5.4.2總線緩沖器1.單向緩沖器5.4.2總線緩沖器1.單向緩沖器LIBRARYIEEE;--第一種方法用兩個進程語句來實現USEIEEE.STD_LOGIC_1164.ALL;ENTITYsingle_buffer_74244ISPORT(en_1,en_2:INSTD_LOGIC;

datain_1,datain_2:INSTD_LOGIC_VECTOR(3DOWNTO0);

dataout_1,dataout_2:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYsingle_buffer_74244;ARCHITECTUREbuffer_74244_method1OFsingle_buffer_74244ISBEGINLIBRARYIEEE;--第一種方法用兩個進程語句method1_1:PROCESS(datain_1,en_1) BEGIN IF(en_1='0')THEN--選通信號是低電平有效的

dataout_1<=datain_1; ELSE dataout_1<="ZZZZ"; ENDIF;ENDPROCESSmethod1_1;method1_2:PROCESS(datain_2,en_2) BEGIN IF(en_2='0')THEN dataout_2<=datain_2; ELSE dataout_2<="ZZZZ"; ENDIF;ENDPROCESSmethod1_2;ENDARCHITECTUREbuffer_74244_method1;method1_1:PROCESS(datain_仿真波形仿真波形2.雙向緩沖器2.雙向緩沖器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdouble_buffer_74245ISPORT(oe,dir:INSTD_LOGIC; dataA,dataB:INOUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYdouble_buffer_74245;ARCHITECTUREbehavioralOFdouble_buffer_74245ISSIGNALoutA,outB:STD_LOGIC_VECTOR(7DOWNTO0);BEGIN LIBRARYIEEE;instA_74245:PROCESS(oe,dir,dataA)--數據從A流向B BEGIN IF((oe='0')AND(dir='1'))THEN outB<=dataA; ELSE outB<="ZZZZZZZZ"; ENDIF; dataB<=outB; ENDPROCESSinstA_74245;

instA_74245:PROCESS(oe,instB_74245:PROCESS(oe,dir,dataB)--數據從B流向A BEGIN IF((oe='0')AND(dir='0'))THEN outA<=dataB; ELSE outA<="ZZZZZZZZ"; ENDIF; dataA<=outA; ENDPROCESSinstB_74245;ENDARCHITECTUREbehavioral;instB_74245:PROCESS(oe,仿真波形仿真波形5.5加法器電路1.半加器5.5加法器電路1.半加器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhalf_adderISPORT(dataA,dataB:INSTD_LOGIC;sum:OUTSTD_LOGIC;carry:OUTSTD_LOGIC);ENDENTITYhalf_adder;ARCHITECTUREdataflowOFhalf_adderISBEGIN sum<=dataAXORdataB;--和數滿足邏輯異或關系

carry<=dataAANDdataB;--進位位滿足邏輯與關系ENDARCHITECTUREdataflow;LIBRARYIEEE;仿真波形仿真波形2.全加器2.全加器LIBRARYIEEE;--直接根據真值表設計USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_adderISPORT(dataA,dataB,carryin:INSTD_LOGIC;sum:OUTSTD_LOGIC;carryout:OUTSTD_LOGIC);ENDENTITYfull_adder;ARCHITECTURErtlOFfull_adderISBEGIN sum<=dataAXORdataBXORcarryin;--和數滿足邏輯異或關系

carryout<=(dataAANDdataB)OR(dataAANDcarryin)OR(dataBANDcarryin);ENDARCHITECTURErtl;LIBRARYIEEE;--直接根據真值表設計仿真波形仿真波形由兩個半加器元件和一個或門構成的全加器由兩個半加器元件和一個或門構成的全加器LIBRARYIEEE;--由兩個半加器元件和一個或門構成的全加器USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_adderISPORT(dataA,dataB,carryin:INSTD_LOGIC;sum:OUTSTD_LOGIC;carryout:OUTSTD_LOGIC);ENDENTITYfull_adder;LIBRARYIEEE;--由兩個半加器元件和一個或門ARCHITECTUREstructOFfull_adderISCOMPONENThalf_adderPORT(a,b:INSTD_LOGIC;s:OUTSTD_LOGIC;ca:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALu1sum,u1carry,u2carry:STD_LOGIC;BEGINu1:half_adderPORTMAP(dataA,dataB,u1sum,u1carry);u2:half_adderPORTMAP(u1sum,carryin,sum,u2carry);carryout<=u2carryORu1carry;ENDARCHITECTUREstruct;ARCHITECTUREstructOFfull4位加法器libraryIEEE;--4位加法器useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;entityadder4bisport(cin:inSTD_LOGIC;a,b:inSTD_LOGIC_VECTOR(3downto0); cout:outSTD_LOGIC;s:outSTD_LOGIC_VECTOR(3downto0));endadder4b;4位加法器libraryIEEE;--4位加法器architectureARCHofadder4bissignalsint,aa,bb:STD_LOGIC_VECTOR(4downto0);BEGINaa<='0'&a(3downto0);bb<='0'&b(3downto0);sint<=aa+bb+cin;s(3downto0)<=sint(3downto0);cout<=sint(4);endARCH;architectureARCHofadder4bi仿真波形仿真波形3.自定制加/減法電路3.自定制加/減法電路5.6求補器電路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;ENTITYcomplementISPORT(datain:INSTD_LOGIC_VECTOR(15DOWNTO0);dataout:OUTSTD_LOGIC_VECTOR(15DOWNTO0));ENDENTITYcomplement;ARCHITECTUREbehavioralOFcomplementISSIGNALtemp:STD_LOGIC_VECTOR(15DOWNTO0);BEGIN temp<=NOTdatain;--對輸入數據取反

dataout<=temp+"0000000000000001";--對反碼加1ENDARCHITECTUREbehavi