課程設(shè)計說明書1引言,如正弦波,三角波,方波和鋸齒波等,因而廣泛用于通信、雷達(dá)、導(dǎo)航、宇航等領(lǐng)域。在本設(shè)計中它能夠產(chǎn)生多種波形，如正弦波,三角波,方波和鋸齒波等，并能實現(xiàn)對各種波頻率和幅度的轉(zhuǎn)變。正由于其在生活中應(yīng)用的重要性，人們它做了大量FPGA、VHDL、單片機(jī)、DOS技能、數(shù)字電路等多種方法實現(xiàn)。,三角波,方波和鋸齒波。且對各種波形的要求如下：依據(jù)按鍵選擇不同的波形〔實現(xiàn)正弦波,三角波,方波和鋸齒波；100Hz-20KHz；各波形頻率可調(diào)〔500Hz；LED數(shù)碼管實時顯示輸出波形的頻率值；用按鍵把握實現(xiàn)輸出信號的幅度調(diào)整〔2.5V5V。1課程設(shè)計說明書2EDAEDAEDA是電子設(shè)計自動化〔ElectronicDesignAutomation〕縮寫。EDA技術(shù)是以HDL〔HardwareDescriptionlanguage〕完成的HDL是相對于一般的計算機(jī)軟件語言，如：C、PASCAL而言的。HDL語言使用與設(shè)計硬件電子系利用HDL程序來描述所期望的電路系統(tǒng)，規(guī)定器件構(gòu)造特征和電路的行為方式；然后利用綜合器和適配器將此程序編程能把握FPGA和CPLD應(yīng)規(guī)律功能的的門級或更底層的構(gòu)造網(wǎng)表文件或下載文件。目前，就FPGA/CPLDHDLABEL-HDL、AHDLVHDL[1]。幾乎全部適于大學(xué)生做的數(shù)字規(guī)律電路試驗都可以在計算機(jī)上利用EDA(ElectronicDesignAutomatic—電子設(shè)計自動化)部配件不能在計算機(jī)上進(jìn)展仿真。因此，在試驗前期階段，即試驗預(yù)習(xí)階段的主要通過虛擬試驗使試驗者在進(jìn)入真實試驗前就能對預(yù)做的試驗有相當(dāng)?shù)牧私?，甚至可以推想到試驗的結(jié)果。這樣在實際做試驗時，可以把很多設(shè)計型試驗的難度降低，同時能有更多的時間讓試驗者動手做試驗，爭論問題，提高試驗效率。當(dāng)前數(shù)字電路設(shè)計已由計算機(jī)關(guān)心設(shè)計進(jìn)入到以計算機(jī)為主的設(shè)計時代。VHDL根本介紹其描述的對象就是待設(shè)計電路系統(tǒng)的規(guī)律功能，實現(xiàn)該功能的算法，選用的電路構(gòu)造以及其他各種約束條件等。通常要求HDL構(gòu)造。801984VHDLIEEE1993IEEEVHDLVHDLVHDL在多級別上對同一規(guī)律功能進(jìn)展描述。VHDLVHDLVHDL2課程設(shè)計說明書設(shè)計方法。設(shè)計工具簡介QuartusII是Altera公司的綜合性PLDVHDLVerilogHDLPLDQuartusIIAlteraIPLPM/MegaFunction方EDA工具的良好支持也使用戶可以在設(shè)計流程的各個階段使用生疏的第三放EDA工具。此外，QuartusIIDSPBuilderMatlab/SimulinkDSPAltera〔SOPC〕開發(fā)，臺。AlteraPLD與AlteraQuartusIIII、ChipEditorRTLViewerMaxplusII友好的圖形界面及簡便的使用方法。AlteraQuartusII和直觀易用的接口，越來越受到數(shù)字系統(tǒng)設(shè)計者的歡送。AlteraQuartusIIPLD一個工作組環(huán)境下的設(shè)計要求，其中包括支持基于InternetQuartusCadence、ExemplarLogic、MentorGraphics、SynopsysSynplicityEDALogicLock模塊設(shè)計功能，增加了FastFit3課程設(shè)計說明書3設(shè)計思想及原理圖基于VHDL據(jù)選擇器實現(xiàn)，四種信號的信號選擇可以用4選1數(shù)據(jù)選擇器實現(xiàn)。同時本設(shè)計使用原理圖的方法，對正弦波、三角波、方波和鋸齒波和41數(shù)據(jù)選擇器元件進(jìn)展調(diào)用。簡易多功能信號發(fā)生器的原理圖如下：1簡易多功能信號發(fā)生器原理圖原理圖本設(shè)計的主題思想是各個模塊分別產(chǎn)生相應(yīng)的波形，再通過一個4選1數(shù)據(jù)選擇器輸出相應(yīng)的波形。通過其他按鍵把握波形的頻率和幅度的變化。正弦波、三角波、方波和鋸齒波的實現(xiàn)正弦波設(shè)計正弦波的產(chǎn)生思想是將對模擬波形采樣后的編碼存入定義好的ROMVHDL代碼如下：libraryieee;useieee.std_logic_1164.all;4課程設(shè)計說明書entitysin2isport(clock,sel:instd_logic;dout4:outintegerrange0to255);endsin2;architecturebhvofsin2istypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(255,254,252,249,245,239,233,225,217,207,197,186,174,162,150,137,124,112,99,87,75,64,53,43,34,26,19,13,8,4,1,0,0,1,4,8,13,19,26,34,43,53,64,75,87,99,112,124,137,150,162,174,186,197,207,217,225,233,239,245,249,252,254,255);signaladdress:integerrange0to63;beginprocess(clock)beginifclock”eventandclock=”1”thenifaddress>63thenaddress<=0;elseifsel=”1”thenaddress<=address+1;dout4<=(mem(address))/2;elseaddress<=address+1;dout4<=mem(address);endif;endif;endif;endprocess;endbhv;正弦波的仿真在QuartusII軟件輸入上述代碼，再通過編譯和時序仿真，可得到如下的仿真5課程設(shè)計說明書波形。2正弦波時序仿真圖上圖中的輸出制式模擬信號各采樣點的數(shù)字編碼，由于沒有經(jīng)過數(shù)模轉(zhuǎn)換，輸三角波設(shè)計三角波的產(chǎn)生思想是將對模擬波形采樣后的編碼存入定義好的ROM中，再依據(jù)VHDL代碼如下：libraryieee;useieee.std_logic_1164.all;entitysanjiaoisport(clock,sel:instd_logic;dout3:outintegerrange0to255);endsanjiao;architecturebhvofsanjiaoistypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,255,248,240,232,224,216,208,200,192,184,176,168,160,152,144,136,128,120,112,104,96,88,80,72,64,56,48,40,32,24,16,8);signaladdress:integerrange0to63;beginprocess(clock)begin6課程設(shè)計說明書ifclock”eventandclock=”1”thenifaddress>63thenaddress<=0;elseifsel=”1”thenaddress<=address+1;dout3<=(mem(address))/2;elseaddress<=address+1;dout3<=mem(address);endif;endif;endif;endprocess;endbhv;三角波的仿真波形。3三角波仿真圖上圖中的輸出制式模擬信號各采樣點的數(shù)字編碼，由于沒有經(jīng)過數(shù)模轉(zhuǎn)換，輸方波設(shè)計方波波的產(chǎn)生思想是將對模擬波形采樣后的編碼存入定義好的ROM中，再依據(jù)VHDL代碼如下：libraryieee;useieee.std_logic_1164.all;entityfangboisport(clock,sel:instd_logic;7課程設(shè)計說明書dout1:outintegerrange0to255);endfangbo;architecturebhvoffangboistypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);signaladdress:integerrange0to63;beginprocess(clock)beginifclock”eventandclock=”1”thenifaddress>63thenaddress<=0;elseifsel=”1”thenaddress<=address+1;dout1<=(mem(address))/2;elseaddress<=address+1;dout1<=mem(address);endif;endif;endif;endprocess;endbhv;方波的仿真波形。8課程設(shè)計說明書4三角波仿真圖上圖中的輸出制式模擬信號各采樣點的數(shù)字編碼，由于沒有經(jīng)過數(shù)模轉(zhuǎn)換，輸鋸齒波設(shè)計鋸齒波的產(chǎn)生思想是將對模擬波形采樣后的編碼存入定義好的ROM中，再依據(jù)VHDL代碼如下：libraryieee;useieee.std_logic_1164.all;entityjuchiisport(clock,sel:instd_logic;dout2:outintegerrange0to255);endjuchi;architecturebhvofjuchiistypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,198,200,204,208,212,216,220,224,228,234,238,242,246,250,255);signaladdress:integerrange0to63;beginprocess(clock)beginifclock”eventandclock=”1”thenifaddress>63then9課程設(shè)計說明書else

address<=0;ifsel=”1”thenaddress<=address+1;dout2<=(mem(address))/2;elseaddress<=address+1;dout2<=mem(address);endif;endif;endif;endprocess;endbhv;鋸齒波的仿真波形。5正弦波未分頻時仿真圖了。各個把握單元的實現(xiàn)頻率把握單元678所示。500Hz。而試驗室的硬件設(shè)備上的按鍵都是撥碼是按鍵，代碼實現(xiàn)按鍵沒按一次都能有效的功能。10課程設(shè)計說明書ifbutton0=”0”andbutton1=”1”thenifcnt=40thencnt<=0;elsecnt<=cnt+1;endif;elsifbutton0=”1”andbutton1=”0”thenifcnt=40thencnt<=0;elsecnt<=cnt+1;endif;6678當(dāng)按下按鍵輸入識別模塊中分別使整個系統(tǒng)輸出最大和最小頻率的波形的把握削減的功能。在分頻數(shù)產(chǎn)生模塊中有一個輸入端接收從按鍵輸入識別模塊中輸出地對頻率號的頻率的輸出端。當(dāng)分頻數(shù)產(chǎn)生模塊的輸入端接收從按鍵輸入識別模塊中輸出地對頻率的把握VHDL代碼見本課程設(shè)計的附錄。分頻器的功能主要是依據(jù)分頻數(shù)產(chǎn)生相應(yīng)的輸出頻率。波形輸出把握單元9所示11課程設(shè)計說明書9數(shù)據(jù)選擇器模塊414個數(shù)據(jù)輸入端，一個數(shù)據(jù)選擇輸入端到輸出端。從而實現(xiàn)數(shù)據(jù)的選擇輸出。硬件測試66個輸出端。具體1中所示。6。另外，本試驗輸12MHz。的值即可得到相應(yīng)的輸出波形。具體的硬件仿真波形如下：clk12MHz1bx[1..0]輸入“00”時10所示。轉(zhuǎn)變sel的值可以該變輸出波形的幅值。按頻率把握單元中介紹的方法可以實現(xiàn)波形頻率的轉(zhuǎn)變。clk12MHz1bx[1..0]輸入“01”時11所示。轉(zhuǎn)變sel的值可以該變輸出波形的幅值。按頻12課程設(shè)計說明書率把握單元中介紹的方法可以實現(xiàn)波形頻率的轉(zhuǎn)變。1bx[1..0]輸入“11”時12所示。轉(zhuǎn)變sel的值可以該變輸出波形的幅值。按頻率把握單元中介紹的方法可以實現(xiàn)波形頻率的轉(zhuǎn)變。13課程設(shè)計說明書附錄方波libraryieee;useieee.std_logic_1164.all;14課程設(shè)計說明書entityfangboisport(clock,sel:instd_logic;dout1:outintegerrange0to255);endfangbo;architecturebhvoffangboistypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);signaladdress:integerrange0to63;beginprocess(clock)beginifclock”eventandclock=”1”thenifaddress>63thenaddress<=0;elseifsel=”1”thenaddress<=address+1;dout1<=(mem(address))/2;elseaddress<=address+1;dout1<=mem(address);endif;endif;endif;endprocess;endbhv;正弦波libraryieee;useieee.std_logic_1164.all;entitysin2isport(clock,sel:instd_logic;15課程設(shè)計說明書dout4:outintegerrange0to255);endsin2;architecturebhvofsin2istypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(255,254,252,249,245,239,233,225,217,207,197,186,174,162,150,137,124,112,99,87,75,64,53,43,34,26,19,13,8,4,1,0,0,1,4,8,13,19,26,34,43,53,64,75,87,99,112,124,137,150,162,174,186,197,207,217,225,233,239,245,249,252,254,255);signaladdress:integerrange0to63;beginprocess(clock)beginifclock”eventandclock=”1”thenifaddress>63thenaddress<=0;elseifsel=”1”thenaddress<=address+1;dout4<=(mem(address))/2;elseaddress<=address+1;dout4<=mem(address);endif;endif;endif;endprocess;endbhv;鋸齒波libraryieee;useieee.std_logic_1164.all;entityjuchiis16課程設(shè)計說明書port(clock,sel:instd_logic;dout2:outintegerrange0to255);endjuchi;architecturebhvofjuchiistypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,198,200,204,208,212,216,220,224,228,234,238,242,246,250,255);signaladdress:integerrange0to63;beginprocess(clock)beginifclock”eventandclock=”1”thenifaddress>63thenaddress<=0;elseifsel=”1”thenaddress<=address+1;dout2<=(mem(address))/2;elseaddress<=address+1;dout2<=mem(address);endif;endif;endif;endprocess;endbhv;三角波libraryieee;17課程設(shè)計說明書useieee.std_logic_1164.all;entitysanjiaoisport(clock,sel:instd_logic;dout3:outintegerrange0to255);endsanjiao;architecturebhvofsanjiaoistypemem_typeisarray(0to63)ofintegerrange0to255;constantmem:mem_type:=(0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,255,248,240,232,224,216,208,200,192,184,176,168,160,152,144,136,128,120,112,104,96,88,80,72,64,56,48,40,32,24,16,8);signaladdress:integerrange0to63;beginprocess(clock)beginifclock”eventandclock=”1”thenifaddress>63thenaddress<=0;elseifsel=”1”thenaddress<=address+1;dout3<=(mem(address))/2;elseaddress<=address+1;dout3<=mem(address);endif;endif;endif;endprocess;endbhv;18課程設(shè)計說明書按鍵輸入識別模塊libraryieee;useieee.std_logic_1164.all;entityaaisport(clk:instd_logic;btn:instd_logic_vector(1downto0);highh:instd_logic;loww:instd_logic;addr:outintegerrange0to40);endaa;architecturebhvofaaissignalcnt:integerrange0to40:=0;signalbutton0,button1,button2,button3:std_logic;beginprocess(highh,loww,clk,button0,button1)beginifclk”eventandclk=”1”thenbutton0<=btn(0);button1<=button0;button2<=btn(1);button3<=button2;ifhighh=”1”thencnt<=40;elsifloww=”1”thencnt<=0;elseifbutton0=”0”andbutton1=”1”thenifcnt=40thencnt<=0;elsecnt<=cnt+1;endif;elsifbutton0=”1”andbutton1=”0”thenifcnt=40then19課程設(shè)計說明書cnt<=0;elsecnt<=cnt+1;endif;elsifbutton2=”0”andbutton3=”1”thenifcnt=0thencnt<=40;elsecnt<=cnt-1;endif;elsifbutton2=”1”andbutton3=”0”thenifcnt=0thencnt<=40;elsecnt<=cnt-1;endif;endif;endif;endif;endprocess;addr<=cnt;endbhv;分頻模塊libraryieee;useieee.std_logic_1164.all;entityfenpinisport(shu:inintegerrange0to937;clk:instd_logic;clock:outstd_logic);endfenpin;architecturebhvoffenpinissignalnum:integerrange0to937;signali:integerrange0to937:=0;signaltemp:std_logic:=”0”;20課程設(shè)計說明書beginprocess(clk,i,temp)beginifclk”eventandclk=”1”thenifi=shutheni<=0;temp<=nottemp;elsei<=i+1;endif;endif;clock<=temp;endprocess;endbhv;分頻數(shù)產(chǎn)生模塊libraryieee;useieee.std_logic_1164.all;entitypinlvisport(address:inintegerrange0to40;shu:outintegerrange0to937;wan,qian,bai,shi,ge:outstd_logic_vector(3downto0));endpinlv;architecturebhvofpinlvisbeginprocess(address)begincaseaddressiswhen0=>shu<=937;wan<=“ZZZZ“;qian<=“ZZZZ“;bai<=“0001“;shi<=“0000“;ge<=“0000“;when1=>shu<=172;wan<=“ZZZZ“;qian<=“ZZZZ“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when2=>shu<=93;wan<=“ZZZZ“;qian<=“0001“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when21課程設(shè)計說明書3=>shu<=62;wan<=“ZZZZ“;qian<=“0001“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when4=>shu<=46;wan<=“ZZZZ“;qian<=“0010“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when5=>shu<=37;wan<=“ZZZZ“;qian<=“0010“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when6=>shu<=31;wan<=“ZZZZ“;qian<=“0011“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when7=>shu<=26;wan<=“ZZZZ“;qian<=“0011“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when8=>shu<=24;wan<=“ZZZZ“;qian<=“0100“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when9=>shu<=20;wan<=“ZZZZ“;qian<=“0100“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when10=>shu<=18;wan<=“ZZZZ“;qian<=“0101“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when11=>shu<=16;wan<=“ZZZZ“;qian<=“0101“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when12=>shu<=15;wan<=“ZZZZ“;qian<=“0110“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when13=>shu<=28;wan<=“ZZZZ“;qian<=“0110“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when14=>shu<=13;wan<=“ZZZZ“;qian<=“0111“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when15=>shu<=12;wan<=“ZZZZ“;qian<=“0111“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when16=>shu<=11;wan<=“ZZZZ“;qian<=“1000“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when17=>shu<=11;wan<=“ZZZZ“;qian<=“1000“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when18=>shu<=10;wan<=“ZZZZ“;qian<=“1001“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when19=>shu<=10;wan<=“ZZZZ“;qian<=“1001“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when22課程設(shè)計說明書20=>shu<=9;wan<=“0001“;qian<=“0000“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when21=>shu<=9;wan<=“0001“;qian<=“0000“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when22=>shu<=8;wan<=“0001“;qian<=“0001“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when23=>shu<=8;wan<=“0001“;qian<=“0001“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when24=>shu<=8;wan<=“0001“;qian<=“0010“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when25=>shu<=7;wan<=“0001“;qian<=“0010“;bai<=“0101“;shi<=“0000“;ge<=“0000“;when26=>shu<=7;wan<=“0001“;qian<=“0011“;bai<=“0000“;shi<=“0000“;ge<=“0000“;when27=>shu<=7;wan<=“0001“;qian<=“0011“;bai<=“010