時(shí)間測(cè)量方法第1頁(yè)/共30頁(yè)2011-05-092SupportedbytheNationalNaturalScienceFoundationofChina(No.10405023)BaseontheprincipleoftimeinterpolationusingthededicatedresourcesofFPGAPatentedin2009AseriesofevaluationboardshavebeendevelopedWithdifferenttypesofFPGAsVitrtexII/IV,Spartan(XILINX)ACEX,Cyclone(ALTERA)Therecentdevelopment:50psinLSB(RMS<25ps)ThemoreeffortofOn-ChipProcessingaimstoimprovetheres.(~10ps)Thefunctionsofself-test,temperaturecompensationandtrigger-matchingareprovidedHasbeenadoptedasthetimemeasurementmethodinseveralfieldsSecureQuantumKeyDistributionatSpaceScaleTheresearchoncoretechnologyforLunarExplorationofChinaHighresolutionTDCbasedonFPGA第2頁(yè)/共30頁(yè)2011-05-093lunarprobeChang'e-3第3頁(yè)/共30頁(yè)2009年，通過(guò)校準(zhǔn)、非線(xiàn)性修正等實(shí)現(xiàn)RMS<25ps的精度目前，在同水平芯片上，已實(shí)現(xiàn)好于10ps精度……2006年，已在FPGA中實(shí)現(xiàn)好于100ps的測(cè)量精度IEEETNS,VOL.53,NO.1(2006),236-241IEEETNS,VOL.57,NO.2(2010),446-450基于FPGA的高精度TDC設(shè)計(jì)第4頁(yè)/共30頁(yè)2011-05-095在FPGA中實(shí)現(xiàn)高精度TDC的手段探討利用游標(biāo)尺型時(shí)間內(nèi)插雙延遲鏈游標(biāo)尺（起停型）雙刻度游標(biāo)尺（時(shí)間戳型）利用延遲線(xiàn)抽頭時(shí)間內(nèi)插時(shí)鐘相位延遲內(nèi)插輸入信號(hào)延遲內(nèi)插第5頁(yè)/共30頁(yè)2011-05-096利用游標(biāo)尺時(shí)間內(nèi)插中實(shí)現(xiàn)的200psTDC——（IEEETRANSACTIONSONINSTRUMENTATIONANDMEASUREMENT,VOL.46,NO.1,FEBRUARY1997）QuickLogicFPGA第6頁(yè)/共30頁(yè)2011-05-097利用延遲線(xiàn)抽頭內(nèi)插實(shí)現(xiàn)高精度TDCINCLKXILINX/ALTERAFPGA第7頁(yè)/共30頁(yè)2011-05-098專(zhuān)用進(jìn)位連線(xiàn)資源ALTERAFPGA第8頁(yè)/共30頁(yè)2011-05-099延遲線(xiàn)抽頭內(nèi)插型TDC框圖（1）第9頁(yè)/共30頁(yè)2011-05-0910基于VME的FPGATDC驗(yàn)證插件AlteraXilinx第10頁(yè)/共30頁(yè)2011-05-0911NIM通用時(shí)間測(cè)量插件第11頁(yè)/共30頁(yè)2011-05-0912通用時(shí)間測(cè)量插件FPGA邏輯第12頁(yè)/共30頁(yè)2011-05-0913時(shí)間內(nèi)插在A(yíng)lteraFPGA實(shí)現(xiàn)的底層視圖ACEX第13頁(yè)/共30頁(yè)2011-05-0914時(shí)間內(nèi)插在A(yíng)lteraFPGA實(shí)現(xiàn)的底層視圖CYCLONE第14頁(yè)/共30頁(yè)2011-05-0915時(shí)間內(nèi)插在XilinxFPGA實(shí)現(xiàn)的底層視圖ACEX第15頁(yè)/共30頁(yè)16Xilinx/AlteraFPGA中TDC測(cè)試結(jié)果用ALTERAEP1C20實(shí)現(xiàn)時(shí)間測(cè)量用XILINXXC3S1600實(shí)現(xiàn)時(shí)間測(cè)量用XILINXXC4VFX60實(shí)現(xiàn)時(shí)間測(cè)量第16頁(yè)/共30頁(yè)2011-05-0917FPGA內(nèi)延遲鏈長(zhǎng)度不夠？雙相/多相時(shí)鐘采樣內(nèi)插ProceedingofTheNinthInternationalConferenceonElectronicMeasurement&Instruments,1-585--1-589第17頁(yè)/共30頁(yè)2011-05-0918延遲線(xiàn)抽頭內(nèi)插型TDC框圖（2）NuclearScienceandTechniques,21(2010)123–128第18頁(yè)/共30頁(yè)2011-05-0919溫度校準(zhǔn)邏輯第19頁(yè)/共30頁(yè)2011-05-0920影響精度提高的因素：分辨率（碼寬）受限于FPGA工藝、結(jié)構(gòu)，無(wú)法改善非線(xiàn)性隨電壓和溫度的變化，碼寬可能變化由于FPGA底層結(jié)構(gòu)，某些碼可能特別寬提高FPGA中TDC時(shí)間測(cè)量精度的方法InCLKUltra-wideBins第20頁(yè)/共30頁(yè)2011-05-0921改善基于FPGA的TDC非線(xiàn)性的途徑非線(xiàn)性的補(bǔ)償（修正）多次測(cè)量求平均WaveUnion/DitherNuclearScienceandTechniques,21(2010)49–53第21頁(yè)/共30頁(yè)2011-05-0922非線(xiàn)性補(bǔ)償83.2957/1.414=58.9ps19.9236/1.414=14.1ps非線(xiàn)性補(bǔ)償前非線(xiàn)性補(bǔ)償后可相對(duì)提高測(cè)量精度但無(wú)法消除過(guò)大的碼寬第22頁(yè)/共30頁(yè)2011-05-0923InCLKWaveUnionLauncher0:Hold01:Unleash1+Ultra-wideBinsUltra-widebinsaresub-divided.WaveUnion(AccordingtoWuJinyuan@Fermilab)第23頁(yè)/共30頁(yè)2011-05-09241:Unleash1212Device:EP2C8T144C6PlainTDC:Max.binwidth:160ps.Averagebinwidth:60ps.WaveUnionTDCA:Max.binwidth:65ps.Averagebinwidth:30ps.WaveUnion方式減小了非線(xiàn)性第24頁(yè)/共30頁(yè)2011-05-0925WaveUnion方式提高了精度PlainTDC:deltatRMSwidth:40ps25pssinglehitWaveUnionTDCA:deltatRMSwidth:25ps17pssinglehit第25頁(yè)/共30頁(yè)2011-05-0926WaveUnionLauncherBInCLK1:Oscillate0:Hold更多次平均的WaveUnion第26頁(yè)/共30頁(yè)TobepublishedonIEEETNS……

2011-05-0927第27頁(yè)/共30頁(yè)2011-05-0928時(shí)間測(cè)量部分的參考文獻(xiàn)(1)ShubinLiu,ChangqingFeng,QiAn,etc.BESIIITime-of-FlightReadoutSystem,IEEETransactionsonNuclearScience,Vol.57,No.2,pp.419-427,APRIL2010;ShubinLiu,ChangqingFeng,LongfeiKang,etc.TheNon-gatedCharge-to-timeConverterfortheTOFDetectorinBESIIINuclearInstrumentsandMethodsinPhysicsResearchA621(2010)pp.513-518;LiuShubin,FengChangqing,YanHan,etc.LUT-basedNon-linearitycompensationforBESIIITOF’stimemeasurement,NuclearScienceandTechniques,21(2010)49–53;XuzongLiu,ShubinLiu,QiAn,Atime-over-thresholdtechniqueforpmtsignalprocessing,NuclearScienceandTechniques,18(3)(2007)1-9;ChangqingFeng,ShubinLiu,QiAn,ElectronicsofBESIIITOFMonitorSystem,IEEETransactionsonNuclearScience,Vol.57,No.2,pp.463-466,APRIL2010;JianSong,QiAn,ShubinLiu,Ahighresolutiontime-to-digital-converterimplementedinfield-programmable-gate-arrays,IEEETransactionsonNuclearScience,Vol.53,No.1,pp.236–241,Feb.2006;JinhongWang,ShubinLiu,QiShen,etc.AFullyFledgedTDCImplementedinField-ProgrammableGateArrays,IEEETransactionsonNuclearScience,Vol.57,No.2,pp.446-450,APRIL2010;LiuShubin,WangJinhong,ChenKai,etc.

DoubleSamplingArchitectureforPerformingFineTimeInterpolationwithinaLimitedLogicDensityFPGA,ProceedingofTheNinthInternationalConferenceonElectronicMeasurement&Instruments,1-585--1-589;ChenKai,LiuShubin,AnQi,Ahighprecisiontiem-to-digitalconverterbasedonmulti-phaseclockimplementedwithinField-Programmable-Gate-Array,NuclearScienceandTechniques,21(2010)123–128JinhongWang,ShubinLiu,LeiZhao,etc.The10-psMulti-TimeMeasurementsAveragingTDCImplementedinanFPGA,tobepublishedonIEEETransactionsonNuclearScience第28頁(yè)/共30頁(yè)2011-05-0929時(shí)間測(cè)量部分的參考文獻(xiàn)(2)J.Christiansen,CERN/EP-MIC,Highperformancetimetodigitalconverter,Mar.2004[Online].Available:http://tdc.web.cern.ch/tdc/hptdc/docs/hptdc_manual_ver2.2.pdf;F.Anghinolfi,P.Jarron,A.N.Martemyanov,E.Usenko,etc.NINO:Anultra-fastandlow-powerfront-endamplifier/discriminatorASICdesignedforthemultigapresistiveplatechamber,Nucl.Instrum.MethodsPhys.Res.,A533183-187(2004).J.Kalisz,R.Szplet,andA.Poniecki,Fieldprogrammablegatearraybasedtime-to-digitalconverterwith200-psresolution,IEEETrans.Instrum.Meas.,vol.46,no.1,pp.51–55,Feb.1997;J.Kalisz,Reviewofmethodsfortime