ComputerOrganization&ArchitectureChapter2

ComputerEvolutionandPerformance2.1ABriefHistoryofComputer4generationsfromcomputerbirth1950~59

Vacuumtube1960~68

Transistor1969~77

IntegratedCircuits

1978~?Large-scaleintegration(LSI)andVery-large-scaleintegration(VLSI)Ch.2-2.1ComputerPre-history

CharlesBabbageAnalyticalEngineApplication–MathematicalTables(Astronomy)andNauticalTables(Navy)Background–AnycontinuousfunctioncanbeapproximatedbyapolynomialTechnology–mechanicalgears,Jacquard’sloom,simplecalculatorsCh.2-2.1Started1943andFinished1946.J.PresperEckert&JohnMauchlyUniversityofPennsylvaniaUseduntil1955Thefirstgeneral-purposecomputer：ENIACCanconditionalJumpandbeprogrammable,distinguisheditfromearlieronesUsedforcomputingartilleryfiringtablesCh.2-2.1ENIAC-detailsDecimal(notbinary)20accumulatorsof10digitsProgrammedmanuallybyswitches18,000vacuumtubes30tons15,000squarefeet140kWpowerconsumption5,000additionspersecondCh.2-2.1VonNeumann/TuringBegin1946,butnotcompleted1952Storedprogramconcept

Mainmemorystoringprogramsand

dataALUoperatingonbinarydataControlunitinterpretinginstructions

from

memoryandexecutingthemInputandoutputequipmentoperatedbycontrolunitPrincetonInstituteforAdvancedStudies–IASCh.2-2.1StructureoftheIAScomputerCh.2-2.1

IAS–details1000x40bitwords（100040bitstorageunits）Binarynumber2x20bitinstructions（8bitopcode，12bitaddress）21instructions:datamove,processing,storage

Setofregisters(storageinCPU)MemoryBufferRegister,MemoryAddressRegister,InstructionRegister,InstructionBufferRegister

ProgramCounter

Accumulator

MultiplierQuotient

ExpandedstructureofIAScomputerCh.2-2.1IAS:InstituteforAdvancedStudy(1952)Ch.2-2.1IASInstructionSet21InstructionsDataTransferUnconditionalBranchConditionalBranchArithmeticAddressModifyCh.2-2.1CommercialComputerLaterof1946,EckertandMauchlyestablishedthefirstcomputercompany--ElectronicControlCorp.TheirfirstsuccessfulmachinewastheUniversalAutomaticComputer(UNIVAC)I.UNIVACtasksinvolvescientificandcommercialapplications.Ch.2-2.1UNIVAC-1(1951)Ch.2-2.1IBM701(1953)Ch.2-2.12ndGeneration:TransistorComputerTransistorInventedin1947atBellLabsSmaller,CheaperandLessheatdissipationSolidstatedevicemadefromSiliconMorecomplexALUandControlUnitsUseofhigherlevellanguagesSystemSoftwareI/OChannelsNCR&RCAarefront-runnersIBM7000series(1952)DEC(PDP-1:firstDECcomputer)Ch.2-2.1IBM7094700seriesin1952lastmemberof7000in1964Memory2Kto32Kof36bitwordsMemoryCycletimefellfrom30microsecto1.4microsecNumberofOpcodesgrewfrom24to185UseofdatachannelsMultiplexortowhichallchannelsareconnectedCh.2-2.1IBM7090ConsoleCh.2-2.13rdgeneration:ICComputerUseofIntegratedCircuits(IC)SSI&MSIbasedcomputeristhe3rdcomputerExamplesIBMSystem/360andDECPDP-8FamilyconceptSimilaroridenticalinstructionsetSimilaroridenticaloperatingsystemIncreasingspeed,increasingnumberofI/Oports,IncreasingmemorysizeandIncreasingcostCh.2-2.1MicroelectronicsIn1958，revolutionizedachievementinelectronicscame:integratedcircuitwasinvented-TheeraofmicroelectronicsTransistor,resistance,capacitancemadefromsemiconductor，togetherwithwholecircuitcanbeputinasiliconwafer60slater,smallscaleintegrationandmediumscaleintegrationcameforthCh.2-2.1IntegratedCircuits(2007state-of-the-art)BareDiePrimarilyCrystallineSilicon1mm-25mmonaside2007featuresize~65nm=65x10-9m(then45,32,22,and16)100-1000Mtransistors25-100M“logicgates”3-10conductivelayers“CMOS”(complementarymetaloxidesemiconductor)-mostcommon.Ch.2-2.1ChipinPackagePrintedCircuitBoardsCeramicorplasticwithgoldwiresPackageprovides:spreadingofchip-levelsignalpathstoboard-levelheatdissipationfiberglassorceramic1-20conductivelayers1-20inonasideICpackagesaresoldereddown.Provides:MechanicalsupportDistributionofpowerandheatCh.2-2.1Moore’sLaw1965，GordonMoore-cofounderofIntelNumberoftransistorsonachipwilldoubleeveryyearSince1970’sdevelopmenthasslowedalittleNumberoftransistorsdoublesevery18monthsCostofachiphasremainedalmostunchangedHigherpackingdensitymeansshorterelectricalpaths,givinghigherperformanceSmallersizegivesincreasedflexibilityReducedpowerandcoolingrequirementsFewerinterconnectionsincreasesreliabilityCh.2-2.1Ch.2-2.1IBM360:AGeneral-PurposeRegister(GPR)MachineCh.2-2.1ProcessorState16General-Purpose32-bitRegistersmaybeusedasindexandbaseregisterRegister0hassomespecialproperties4FloatingPoint64-bitRegistersAProgramStatusWord(PSW)A32-bitmachinewith24-bitaddressesButnoinstructioncontainsa24-bitaddress!DataFormats8-bitbytes,16-bithalf-words,32-bitwords,64-bitdouble-wordsCh.2-2.1DECPDP-8(1965)FirstminicomputerDidnotneedairconditionedroomSmallenoughtositonalabbench$16,000-$100k+forIBM360Bus

structureCh.2-2.1DECPDP-8Ch.2-2.14G：LSI&VLSIComputer

Semiconductormemories64MBperchipMicroprocessorsInstructionset>150Addressbuswidth32DataBuswidth32Memoryaddressability4GBBusbandwidth32MB/secCachearchitecturesCh.2-2.1Intel4004DieIntroducedin1970Firstmicroprocessor2,250transistors12mm2108KHzCh.2-2.1Intel8086DieIntroducedin197929,0000transistors33mm25MHzBasicarchitectureoftheIA32PCCh.2-2.1Intel80486DieIntroducedin19891,200,000transistors81mm225MHz1stpipelinedimplementationofIA32PCCh.2-2.1PentiumDieIntroducedin19933,100,000transistors296mm260MHz1stsuperscalarimplementationofIA32Ch.2-2.1PentiumIII9,5000,000transistors125mm2450MHzIntroducedin1999SuperscalarprocessingCh.2-2.1IntelMicroprocessors1971-4004FirstmicroprocessorAllCPUcomponentsonasinglechip4bitFollowedin1972by80088bit1974–8080Intel’sfirstgeneralpurposemicroprocessor8086、8088、80286、80386、80486、pentium1、2、3、4Xeon(2001),Centrino,Itanium1,2,CoreCh.2-2.1SummaryonsingleCoreRISCRevolution

~1983,IBM801,UCBRISCproject,StanfordMIPSproject

-MakethemicroenginebetheCPU!

-Avoidinefficiencyofinterpretationlayer-Letcompilersdotheoptimizing-ImplementonsinglechipGenericUnixBoxCh.2-2.1SuperscalarProcessing~1990(IBMPower-1)topresent(almostallprocessorstoday)Basicidea:issuemultipleinstructionssimultaneously

-exploitfine-grainedparallelismwithintheinstructionstreamIn-order(Alpha21164)vs.out-of-order(MIPSR10K,PentiumPro)Aggressive,pipelinedcacheandmemorysubsystemsCh.2-2.1QuantityandUnitincommonuseBitByteK(Hz,bytes)：--1024＝210M:Mega(bytes,Hz)：--10242＝220G:Giga(bytes,Hz):--10243＝230T:tera(bytes，Hz):--10244＝240P:peta(bytes，Hz):--10245＝2502.2DesigningforPerformanceMicroprocessorspeedCPU/memorycapacityfollowsMoore’slaw

SeenextFig.ThetechniquesformeettheCPUspeedBranchpredicionDataflowanalysisSpeculativeexecutionMemoryspeedlagsofCPU’sspeed

CPUhastowaitBottleneckReducethewholeperformanceCh.2-2.2DRAMandProcessorCharacteristicsCh.2-2.2SolutionsOptimizesystemstructure,balancingthewholeperformanceofCPU,memoryandI/OImprovetheinterfacebetweenCPUandmemoryTheinterfaceisthekeypathresponsiblefortransferringinstructionanddata

IncreasenumberofbitsretrievedatonetimeMakeDRAM“wider”ratherthan“deeper”ChangeDRAMinterfaceCacheReducefrequencyofmemoryaccessMorecomplexcacheandcacheonchipIncreaseinterconnectionbandwidthHighspeedbusesHierarchyofbusesCh.2-2.2EvolutionofPentium8080：thefirstgeneralpurposeCPUintheworld8bit,19748086(8088)：16bit，Cache，1Mmainmemory；80286：extendedproductof808816Mmainmemory80386：32bit，multi-taskprocessor；80486：highperformanceCache，pipeline,mathcoprocessor;Pentium:Superscalar,instructionexecutedinparellel;Pentiumpro:branchprediction,dataflowanalysis,speculativeexecutionPⅡ：32bit.64bitinstructions：MMX；PⅢ：newfloatpointinstructions:128bit:SSE,support3-dgraphicsprocessingPⅣ：32bit.Providing128bitinstructions:SSE2Ch.2-2.2ClassificationofComputersSingle-chipSingle-boardMicrocomputerMinicomputerMediumcomputerLargecomputerSupercomputerCh.2-2.2RelationshipbetweensoftwareandhardwareCh.2-2.2SofthierarchiesofaComputerapplicationlanguage high-levellanguageassemblylanguageOS(jobcontrollanguage)machinelanguage(machineinstructionsystem)microprogram(microinstructionsystem)