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1、CHAPTER 8Answer Key8-13(P719)The counting direction is controlled by QD: count up when QD=1, count down when QD=0. A load occurs when the counter is in the terminal state, 1111 when counting up, 0000 when counting down. The MSB is complemented during a load and the other bits are unchanged.8-13(P719

2、)Let us assume that the counter is initially in one of the states 00000111. Then the counter counts down(QD=0). Upon reaching state 0000, it loads 1000 and subsequently counts up (QD=1). Upon reaching state 1111, the counter loads 0111, and subsequently counts down, repeating the cycle.8-13(P719)If

3、the counter is initially in one of the states 10001111, the same cyclic behavior is observed. The counting sequence has a period of 16 and is, in decimal,8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, 1, 0, 8, 9, .8-42To get even spacing(平均的間隔), the strategy is for the MSB (N3) to select half the s

4、tates, the ones where QA is 0. The next bit down (N2) selects one-fourth of the states, the ones where QB is 0 and the less significant counter bits (i.e.,QA) are all 1. Likewise, N1 selects the one-eighth of the states where QC is 0 and QB and QA are 1, and N0 selects the state where QD is 0 and QC, QB, and QA are all 1. In this

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