1、精選優質文檔-傾情為你奉上Author:-Engineer Lhrace1、半整數分頻占空比不為50%/說明：設計的史上最好用的半整數分頻占空比不為50%，包含設計思路module div_5(clk,clk_div,cnt1,cnt2,temp1,temp2);/N+0.5input clk;output clk_div;output reg31:0cnt1,cnt2;output reg temp1,temp2;initial begin temp1=0;temp2=1;end /首先進行初始化，temp1=0;temp2=1parameter N=5; /設定分頻系數為N+0.5alwa

2、ys (posedge clk) /temp1上升沿跳變beginif(cnt1=2*N) /2*Nbegin cnt131:0<=32'd0;endelse begin cnt131:0<=cnt131:0+32'd1;endif(cnt1=32'd0) begin temp1<=1;end /高電平時間為N+1;if(cnt1=N+1) begin temp1<=0;end /低電平時間為N;endalways(negedge clk) /temp2下降沿跳變beginif(cnt2=2*N) /2*Nbegin cnt231:0<=3

3、2'd0;endelse begin cnt231:0<=cnt231:0+32'd1;endif(cnt2=32'd0) begin temp2<=0;end /低電平時間為N;if(cnt2=N) begin temp2<=1;end /高電平時間為N+1;endassign clk_div=temp1&&temp2; /邏輯與endmodule /如果要進行N+0.5分頻/思路：總的來說要進行N+1+N=2N+1次分頻/在時鐘的上升沿和下降沿都進行跳變/上升沿進行占空比為N+1比N的時鐘temp1;/下降沿進行占空比為N比N+1的

4、時鐘temp2;/最后div=temp1&&temp2 即可得到所需要的半整數分頻分頻5.5仿真結果2、奇數分頻占空比為50%/說明：奇數分頻。module div_5(clk,clk_div,cnt1,cnt2,temp1,temp2);/input clk;output clk_div;output reg31:0cnt1,cnt2;output reg temp1,temp2;parameter N=5; /設定分頻系數always (posedge clk)beginif(cnt1=N-1) /N-1進行N計數begin cnt131:0<=32'd0;e

5、ndelse begin cnt131:0<=cnt131:0+32'd1;endif(cnt1=32'd0) begin temp1<=1;end /if(cnt1=(N-1)/2) begin temp1<=0;end /當計數到(N-1)/2時翻轉endalways(negedge clk)beginif(cnt2=N-1) /N-1begin cnt231:0<=32'd0;endelse begin cnt231:0<=cnt231:0+32'd1;endif(cnt2=32'd0) begin temp2<

6、=1;end /;if(cnt2=(N-1)/2) begin temp2<=0;end /當計數到(N-1)/2時翻轉;endassign clk_div=temp1|temp2; /邏輯或endmodule2任意小數分頻 Module xiao_fenpin(clk,divclk);/占空比為50%任意小數分頻input clk;reg clkout;reg delete;parameter k=10;reg k-1:0p;parameter M=13;/ clk輸入的頻率，parameter N=11;/需要得到的頻率/假如是13Mhz,要生成一個11M的頻率 /占空比為50%/由

7、M時鐘分頻等到N頻率的方法。 always(posedge clk)begin if(p>=M)begin pk-1:0<=pk-1:0-M+N;delete<=1'b0;endif(p<M) begin pk-1:0<=pk-1:0+N;endif(N<=p&&p<M)begin delete<=1'b1;endendalways(delete)/刪除脈沖，相當于合并脈沖beginif(delete=1)clkout<=1;elseclkout<=clk;endreg cnb;wire cnc;output divclk;assign cnc=cnb&&clk;assign divclk=!cnc&&clkout;always (posedge clk)begin if(delete=1)cnb<=1;else cnb<=0;endendmodule /output reg 5:0cnt1,cnt2; /cnt1,cnt2用于驗證脈沖是否準確/always (posedge clk)/begin /if(cnt1=M-1)/cnt1<=0;/el