1、三角波及階梯波實(shí)驗(yàn)報(bào)告 1、 功能描述 二、元件及其VHDL代碼1、三角波代碼、波形仿真及元件signal3library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity signal3 is-三角波signal3port(clk,reset:in std_logic;-復(fù)位信號(hào)reset，時(shí)鐘信號(hào)clkq:out std_logic_vector(7 downto 0);-輸出信號(hào)q，8位數(shù)字信號(hào)end signal3;architecture a of signal3 isbeginproces

2、s(clk,reset)variable tmp:std_logic_vector(7 downto 0);variable a:std_logic;beginif reset='1' thentmp:="00000000"elsif rising_edge(clk)thenif a='0' then-a=0，實(shí)現(xiàn)加法計(jì)數(shù)if tmp="11111110" thentmp:="11111111"-加法計(jì)數(shù)全1時(shí)，令a=1a:='1'elsetmp:=tmp+1;-加法計(jì)數(shù)end if;e

3、lseif tmp="00000001" thentmp:="00000000"-減法計(jì)數(shù)全0時(shí)，令a=0a:='0'elsetmp:=tmp-1;-減法計(jì)數(shù)end if;end if;end if;q<=tmp;-信號(hào)輸出，產(chǎn)生三角波end process;end a; 2、 階梯波代碼、波形仿真及元件signal4library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity signal4 is-階梯波signal4port(clk

4、,reset:in std_logic;-復(fù)位信號(hào)reset，時(shí)鐘信號(hào)clkq:out std_logic_vector(7 downto 0);-輸出信號(hào)q，8位數(shù)字信號(hào)end signal4;architecture a of signal4 isbeginprocess(clk,reset)variable tmp:std_logic_vector(7 downto 0);beginif reset='1' thentmp:="00000000"elsif rising_edge(clk)thenif tmp="11111111"

5、thentmp:="00000000"elsetmp:=tmp+16;-階梯信號(hào)的產(chǎn)生，階梯變化值=16end if;end if;q<=tmp;end process;end a; 3、 數(shù)據(jù)選擇器代碼及元件shujuxuanzeqilibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shujuxuanzeqi isport(sel:in std_logic_vector(2 downto 0);-選擇信號(hào)seld1,d2,d3,d4,d5,d6:in std

6、_logic_vector(7 downto 0);-6路輸入信號(hào)q:out std_logic_vector(7 downto 0);-被選擇信號(hào)輸出end shujuxuanzeqi;architecture a of shujuxuanzeqi isbeginprocess(sel)begincase sel iswhen "001"=>q<=d1;-選擇信號(hào)sel=001，選擇第1路信號(hào)輸出when "010"=>q<=d2;-選擇信號(hào)sel=010，選擇第2路信號(hào)輸出when "011"=>q<=d3; -選擇信號(hào)sel=011，選擇第3路信號(hào)輸出when "100"=>q<=d4; -選擇信號(hào)sel=100，選擇第4路信號(hào)輸出when "101"=>q<=d5; -選擇信號(hào)sel=101，選擇第5路信號(hào)輸出when "110"=