1、1Chapter 8 Counters (and the Sequential Logic)2Contentsw Introductionw Analysis of the Sequential Logicw Countersw Design of Sequential Logics38-0 Introductionw The digital electronic logic is classified as the combinational logic and the sequential logic. w (數字電路分為：數字電路分為：組合邏輯電路及時序邏輯電路組合邏輯電路及時序邏輯電路

2、)w The sequential logic includes the combinational logic section and the memory section.48-0 Introduction The logic diagram for the general sequential logic輸出方程驅動方程狀態方程58-0 Introductionw The sequential logic is classified as the asynchronous one and synchronous one (異步時序異步時序電路和同步時序電路）電路和同步時序電路）.w Th

3、e analysis and design of the sequential logic is discussed in this chapter. And the counter is the most useful device.68-2 Synchronous Counter Operation (同步計數器）& Analysis of the Sequential Logic（時序電路分析）w Synchronous (同步同步): Events that have a fixed time relationship with each other.w Synchronous

4、 counter: the counter whose flip-flop (FF) are clocked at the same time by a common clock pulse.78-2-1 Analysis of the Sequential Logicw Whats the function of the following logic diagram?How to analyze this diagram? 88-2-1 Analysis of the Sequential Logic -ProcedureProcedure: Write down the clock an

5、d excitation expressions for each FF.2. Get their state expressions by replacing the logic expression for the FF with its excitation expression.寫出每個觸發器的時鐘方程和驅動方程；寫出每個觸發器的時鐘方程和驅動方程；2. 2. 將驅動方程代入觸發器的特性方程，得到狀態方程組；將驅動方程代入觸發器的特性方程，得到狀態方程組；98-2-1 Analysis of the Sequential Logic -Procedure3. 3. 寫出輸出方程；寫出輸

6、出方程；5. 5. 說明電路的邏輯功能。說明電路的邏輯功能。4. 4. 依次假定依次假定初態初態, ,計算計算次態次態, ,畫出畫出狀態轉換圖狀態轉換圖( (表表) )或或 時序波形圖時序波形圖 。3. Write down the output expression;4. Assume the present state, and analyze the next state, and draw its state diagram (狀態轉換圖狀態轉換圖) /state sequence table(狀態轉換表狀態轉換表)or its timing diagram （時序圖）（時序圖）.5.

7、 Determine the logic function of the logic diagram.108-2-1 Analysis of the Sequential Logic Example1w Ex.1 Determine the logic function.01100101)(. 1QKJKJCLKCPCPSynchronous Sequential LogicWrite down the clock and excitation expressions for each FF.Toggle at the positive edge.nnnQKQJQ1. 2)()(. 21010

8、11010CLKQQQQQCLKQQnnnnnnnT FFJ=K=1118-2-1 Analysis of the Sequential Logic Example14. Assume the present sate, and analyze the next state, and draw its state diagram / state sequence table or its timing diagram.)()(. 2101011010CLKQQQQQCLKQQnnnnnnn128-2-1 1 Analysis of the Sequential Logic State Sequ

9、ence Table (狀態轉換表)1001QQ1101QQ0001QQ0101QQ)()(. 2101011010CLKQQQQQCLKQQnnState Sequence Table138-2-1 Analysis of the Sequential Logic State Diagram (狀態轉換圖)State Sequence TableState Diagram148-2-1 Analysis of the Sequential Logic Timing Diagram (時序圖)Timing Diagram158-2-2 A 2-Bit Synchronous Binary Co

10、unterA 2-bit synchronous binary counter(2位同步二進制位同步二進制/4進制進制 加法計數器）加法計數器）168-2-3 A 3-Bit Synchronous Binary Counterw Ex.2 Determine the logic function.178-2-3 A 3-Bit Synchronous Binary Counter188-2-3 A 3-Bit Synchronous Binary CounterA 3-bit synchronous binary counter(3位同步二進制位同步二進制/8進制進制 加法計數器）加法計數器

11、）198-2-4 A 4-Bit Synchronous Decade Counter208-2-4 A 4-Bit Synchronous Decade Counter218-2-4 A 4-Bit Synchronous Decade CounterA 1-bit synchronous decade counter(同步十進制加法計數器）同步十進制加法計數器）228-1 Asynchronous Counter Operation (異步計數器異步計數器)w Asynchronous: refers to events that do not have a fixed time rela

12、tionship with each other and, generally, do not occur at the same time.w Asynchronous counter: counter in which the FF do not change states at exactly the same time because they do not have a common clock pulse.238-1-1 Analysis of Asynchronous Sequential Logicw Determine the logic function.Asynchron

13、ous Sequential Logic248-1-1 Analysis of Asynchronous Sequential Logic)()()()(exp. 103120100QCPQCPQCPcpCPressionsClock258-1-1 Analysis of Asynchronous Sequential Logic1,11,1)2(32132213100KQQJKJKQJKJnnnQKQJQ1. 2)()()()(. 20321131212013110010QQQQQQQQQQQQcpQQnnnn268-1-1 Analysis of Asynchronous Sequenti

14、al Logic30. 3QQC 278-1-1 Analysis of Asynchronous Sequential Logic)()()()(. 20321131212013110010QQQQQQQQQQQQcpQQnnnn30. 3QQC 288-1-1 Analysis of Asynchronous Sequential LogicState Sequence TableState DiagramA asynchronous decade counter(異步十進制加法計數器）異步十進制加法計數器）298-1-2 Some Useful Conceptsw Valid state

15、s (used states) (有效狀態) states used by the diagram in normal operation.w Invalid states (unused states)(無效狀態） states which arent used by the diagram in normal operation.308-1-2 Some Useful ConceptsValid StatesInvalid StatesValid CycleInvalid Cycle318-1-2 Some Useful Conceptsw Valid Cycle (有效循環) Cycle

16、 that includes the valid states.w Invalid Cycle(無效循環） Cycle that includes the invalid states.328-1-2 Some Useful Conceptsw Startup automatically (自啟動功能) If a logic diagram doesnt have invalid cycle(無效循環), it can startup automatically. ( (電路進入無效狀態之后電路進入無效狀態之后, ,在在CPCP脈沖作用下脈沖作用下, ,能自動返回有能自動返回有效循環效循環,

17、,稱電路能夠自啟動稱電路能夠自啟動, ,否則為不能自啟動）否則為不能自啟動）w Self-startup check (自啟動檢查) Check if all the invalid states can enter the valid cycle automatically. 33State DiagramStartup automaticallySelf-startup check348-3 Counters 8-3-1 Categories of CountersOthers）(counter Up/Down ）( counter Down ）( counter Up可逆計數器減法計數器

18、加法計數器The counter can be classified as the following categories:）( counter sSynchronou）( counter usAsynchrono同步計數器異步數器358-3-1 Categories of Counters）( counter Others）( counter Decade）( counter Binary 其他計數器十進制計數器二進制計數器Modulus-2 counter (2進制）進制）Modulus-10 counter (10進制）進制）Modulus-60 counter (60進制）進制）Mo

19、dulus-M counter (M進制進制,任意進制）任意進制）368-2-5 Synchronous Binary CountersQn+1=TQn+TQnC=Q0Q1Q2Q3Negative edge- triggered 378-2-5 Synchronous Binary Countersf01/2f01/4f01/8f01/16f01/16f0The counter is also called the frequency divider (分頻器分頻器).C=Q0Q1Q2Q3388-2-5 Synchronous Binary Counters -74161 MSI modulu

20、s-16 counterCounter, Divider,Modulus-16(16進制進制)398-2-5 74161 MSI modulus-16 counterParallel data inputs( (并行輸入端）并行輸入端） Data outputs/States Clock PulseActive at the positive edgeENT,ENP: Enable Pins 408-2-5 74161 MSI modulus-16 counter418-2-5 74161 MSI modulus-16 counterPreset input (Load)(預置端）預置端）(同

21、步預置同步預置)Active-low, synchronously Clear input (清零端）清零端）(異步清零異步清零)Active-low, asynchronously 428-2-5 74161 MSI modulus-16 counterAt the terminal count of 15, RCO=1.Ripple clock output(進位脈沖進位脈沖)438-2-5 74161 MSI modulus-16 counterState DiagramTiming Diagram448-2-5 74161/74163 MSI modulus-16 counterCLR

22、LOADENPENTLogic Function Table(功能表）功能表） for 74161/74163458-2-5 74161/74163 MSI modulus-16 counterClear input (清零端）清零端）(異步清零異步清零)Active-low, asynchronously 468-2-5 74161/74163 MSI modulus-16 counterPreset input (Load)(預置端）預置端）(同步預置同步預置)Active-low, synchronously 478-2-5 74161/74163 MSI modulus-16 coun

23、terOnly when both of EP and ET are active, is the counter enabled (in counter operation).The outputs plus one at the positive-edge of CP 488-2-5 74161/74163 MSI modulus-16 counterOnly when both of EP and ET are active, is the counter enabled (in counter operation).498-2-5 74160 MSI modulus-10 counte

24、r74160 synchronous BCD decade counter (CTR DIV 10 modulus-10, 10 states)508-2-5 74160 MSI modulus-10 counterClear asynchronously 異步清零異步清零The clear input is active-LOW.518-2-5 74160 MSI modulus-10 counterA timing diagram showing the counter being preset to count 7 (0111).Preset synchronously 同步預置同步預置

25、When the preset input is nonactive, the parallel inputs have no use.The outputs are preset to the corresponding data input only at the active edge of CP.528-2-5 74160 MSI modulus-10 counterWhen the terminal count is 9 (TC=9), RCO=1538-2-5 74160 MSI modulus-10 counterIf any of ENP and ENT is nonactiv

26、e (LOW), the outputs are disabled, remain in present states548-3 Up/Down Synchronous Counters(可逆可逆/加減計數器加減計數器)w By the control of the up/down input, the counter, on one hand, can increase one by one; on the other hand, can also decrease one by one.w This kind of counter is called up/down (加減加減) one,

27、 bidirectional （可逆）（可逆）counter, also.558-3 Up/Down Synchronous CountersA basic 3-bit up/down synchronous counter568-3 Up/Down Synchronous CountersUp/down sequence for a 3-bit binary counterState Sequence Table for a 3-bit binary counter578-3 Up/Down Synchronous CountersState DiagramUp sequenceDown s

28、equence588-3 Up/Down Synchronous Countersw Logic function table for MSI 74191- a synchronous modulus-16 up/down counterPreset Asynchronously 異步預置異步預置LOADCTEN598-3 Up/Down Synchronous Countersw Logic symbol for MSI 74190- a synchronous modulus-10 up/down counter608-3 Up/Down Synchronous CountersTimin

29、g Example For a 74190Preset Asynchronously 異步預置異步預置618-4 Design of Sequential Logics(時序電路設計)Sequential logic designSSI Sequential logic design(小規模小規模)- Design sequential logic using flip-flops 用觸發器設計時序電路用觸發器設計時序電路MSI Sequential logic design(中規模中規模)- Design modulus-M counter using MSI modulus-N count

30、er用用N進制中規模集成計數器設計任意進制中規模集成計數器設計任意M進制計進制計數器數器628-4-1 SSI Sequential logic design- Sequential Logics Design using FFProcedure:w Step 1: Convert the given problem to a logic problem. Assume the input, output and state variables.w Step 2: Get its state diagram.w Step 3: Get its state sequence table.w St

31、ep 4: According to the number of the states, draw a corresponding number-variable K-map. 638-4-1 Sequential Logics Design using FFw Step 5: Get the state expressions using K-map.w Step 6: Choose the needed flip-flop. w Step 7: Get the excitation expressions according to the state expressions and log

32、ic expression for the corresponding flip-flop.w Step 8: Sketch the logic diagram.648-4-1 Sequential Logics Design using FFExample 1Ex.1: Design a modulus-13 counter with cascaded output.Step 1: Assume the input, output and state variables. Output: CState variables: S0,S1S12State diagram.658-4-1 Sequ

33、ential Logics Design using FFExample 113 states: 4 flip-fops (13 =24)Step 2: State sequence table.668-4-1 Sequential Logics Design using FFExample 1w Step 3: next-state K-map.Present state:0000Next state: 0001 Output: 0Dont care conditions678-4-1 Sequential Logics Design using FFExample 1w Step 4: G

34、et k-map for each state. (Optional)688-4-1 Sequential Logics Design using FFExample 1Step 5: Get the state expressions.698-4-1 Sequential Logics Design using FFExample 1Step 5: Get the output expression.C=Q3Q2Step 6: Choose the flip-flop: J-K flip-flop.708-4-1 Sequential Logics Design using FFExampl

35、e 1Step 7: Get the excitation expression.nnnQKQJQ113323210QQQQQQQn718-4-1 Sequential Logics Design using FFExample 1Step 8: Draw the logic diagram.C=Q3Q2728-4-1 Sequential Logics Design using FFExample 1w Step 9: Self-startup check (自啟動檢查自啟動檢查)It can startup automatically.13323210QQ QQ Q Q Qn738-4-1

36、 Sequential Logics Design using FFExample 2Ex. 2: Design a logic diagram that can check the series data. When there are three or more than three HIGH inputs in series, the output is 1; otherwise , the output is 0. 設計一個串行數據檢測器。當連續輸入設計一個串行數據檢測器。當連續輸入3個或個或3個以上個以上1的時候，輸出為的時候，輸出為1；否則為；否則為0。 748-4-1 Seque

37、ntial Logics Design using FFExample 2w Step 1: Analyze the problem, assume the input/output variables, and get its state diagram/state sequence table.Assume:X: the input variable;Y: the output variable;States: S0 the input is 0; S1 there is only one HIGH input. S2 there is two HIGH inputs in series.

38、 S3 there is three or more than three HIGH inputs in series.758-4-1 Sequential Logics Design using FFExample 2w Step 2: State sequence tableEquivalent States(等價狀態等價狀態)The input768-4-1 Sequential Logics Design using FFExample 2Step 3: K-map0001103 states: 2 flip-fops (3 N, more than one MSI device is

39、 needed.1088-4-3 Sequential Logics Design using MSI Counterw1. MNSkip N-M statesTwo methods:(1) Implement it using the CLEAR (RESET) input (generally the CLEAR input is asynchronous). (利用清零端，反饋歸零法)(2) Implement it using the PRESET input. (Some of the PRESET input are asynchronous, and others are syn

40、chronous) (利用預置端，置數法)1098-4-3 Sequential Logics Design using MSI CounterMomentary/Astable state (瞬態), not included in the valid cycle.異步清零，瞬態不包括在有效循環中異步清零，瞬態不包括在有效循環中Preset the states at any state可在任意狀態下進行預置可在任意狀態下進行預置同步預置沒有瞬態，異頻預置有瞬態。同步預置沒有瞬態，異頻預置有瞬態。1108-4-3 Sequential Logics Design using MSI Coun

41、terOnly when both of EP and ET are active, is the counter enabled (in counter operation).w Ex. 1 Implement a modulus-6 counter using 74160.w Logic Function Table for 74160Clear inputActive-low, asynchronously(異步清零) Preset input (Load)Active-low, synchronously(同步預置) 1118-4-3 Sequential Logics Design using MSI C