1、LTspice1. 變壓器仿真的簡單步驟:A.為每個變壓器繞組繪制一個電感器B.采用一個互感(K)描述語句通過一條 SPICE指令對其實施耦合:K1 L1 L2 1K語句的最后一項是耦合系數，其變化范圍介于0和1之間，1代表沒有漏電感。對于實際電路，建議您采用耦合系數 =1作為起點每個變壓器只需要一個K語句；LTspice為一個變壓器內部的所有電感器應用了單一耦合系數。下面所列是上述語句的等效語句：K1 L1 L2 1K2 L2 L3 1K3 L1 L3 1C. 采用 移動” (F7)旋轉” (Ctrl + R)和 鏡像” (Ctrl + E)命令來調 節電感器位置以與變壓器的 極性相匹配。添

2、加 K語句可顯示所含電感器的調相點。D. LTspice采用個別組件值(在本場合中為個別電感器的電感)而非變壓器的匝數比進行變壓器的仿真。電感比與匝數比的對應關系如下：電感至匝數比例如：對于1:3和1:2的匝數比，輸入電感值以產生1:9和1:4的比值：2. 一般來說壓是對地，如果你想知某元件倆端的電壓該如何呢？設一參考點，先點小人，然后在電路圖的空白處點右鍵，找黑白電筆Set probe reference,也可從VIEW 找。按鍵盤上ESC可去黑白電筆。3. Die Impulsantwort 脈沖響應。4. To create an LTspice model of a given MOS

3、FET, you need the original datasheet and the pSPICE model of that MOSFET.The parameters needed to define a MOSFET in LTspice are as follows:RgGate ohmic resistanceRd Drain ohmic resistance (this is NOT the RDSon, but the resistance of the bond wire)RsSource ohmic resistance.VtoZero-bias threshold vo

4、ltage.Kp - Transconductance coefficientLambda Change in drain current with VdsCgdmax Maximum gate to drain capacitance.Cgdmin Minimum gate to drain capacitance.CgsGate to source capacitance.CjoParasitic diode capacitance.IsParasitic diode saturation current.RbBody diode resistance.Rg, Rd and Rs are

5、the resistances of the bond wires connecting the die to the package.Vto is the turn on voltage of the MOSFET.Kp is the transconductance of the MOSFET. This determines the drain current that flows for a given gate source voltage.Lambda is the change in drain current with drain source voltage and is u

6、sed with Kp to determine the RDSon.Cgdmax and Cgdmin are the minimum and maximum values of the gate drain capacitance and are normally graphed in the MOSFET datasheet as Crss. The capacitance of a capacitor is inversely proportional to the distance between its plates. When the MOSFET is turned on, d

7、istance between the gate and the conducting channel of the drain is equal to the thickness of the insulating gate oxide layer (which is small) so the gate drain capacitance is high. When the MOSFET is turned off, the gate drain region is large, making the gate drain capacitance low. This can be seen

8、 on the plot of Crss.Cgs is the gate source capacitance. Although it changes slightly with gate source voltage, LTspice assumes it is constant.Is is the parasitic body diode saturation current.Rb is the series resistance of the body diode.The Fairchild FDS6680A MOSFET is defined in LTspice by the li

9、ne.model FDS6680A VDMOS(Rg=3 Rd=5m Rs=1m Vto=2.2 Kp=63 Cgdmax=2n Cgdmin=1n Cgs=1.9nCjo=1n Is=2.3p Rb=6m mfg=Fairchild Vds=30 Ron=15m Qg=27n)Note: the characteristics Vds, Ron and Qg are actually ignored by LTspice. These are only added to aid the user to compare MOSFETs.Therefore an example template

10、 MOSFET model is.model XXXX VDMOS(Rg= Rd=5 Rs=1 Vto= Kp= Cgdmax= Cgdmin= Cgs= Cjo= Is= Rb=)We are now going to construct a MOSFET model for the SUM75N06 and SUM110N04 low ON resistance MOSFETs from VishaySUM11CNC4JcharacteristicoiurceValueChoracteritiDSourceValue|Rbanother SPICE model1.5 GhmsF.banot

11、iier 5PICE modeli.S OhmsIRd5PICE modelRdSPICE mcd&ln Ohrn?RsSrC£ model2Etn OhmssPtCE tn addC 36tti Ohns |vtoDatasheet刃vroDcidisheei1 85V即Datasheet75 5噸Dctsheet190 SLambdaSPICE default value1Lambda=pCE default uaLe1CgdirkakCrss curve12DOpFCgcrndMDatasheet Crss 匚tm34叩FcgJiiinDatasl eel crss c

12、urve150pFCgdrnrDatasheet Crss curvegoopF耶SPtCE model20DOpF呻SPCCE nipdri14-ErFCjo5PICE modellOOpFCjoGPKE mt del4.9rFItEPICE mocfelIpATSSPDCE mod Bi33.4pARbSPtCE dufajlt va ue3 Ohms口 tlSPCE lEbault ualLe0 Dhms.model SUM75N06-09L VDMOS(Rg=1.5 Rd=0m Rs=25m Vto=2.0 Kp=75 Cgdmax=1.2n Cgdmin=150p Cgs=2nCjo

13、=1.2n Is=1p Rb=0).model SUM110N04 VDMOS(Rg=1.5 Rd=0m Rs=0.86m Vto=1.85 Kp=180 Cgdmax=3n Cgdmin=900pCgs=14.5n Cjo=4.9n Is=33.4p Rb=0)The SPICE models can then be testing using these test jigs:RDSon test jig為了測試 MOSFET 的 Rdson,在 LTspice 中導入測試電路。Check the datasheet to see how the FDson has beentested.

14、It will be characterised with a certain gate-source voltage and a certain drain current.Run the simulation. Probe the drain voltage. Probe the drain current. Edit the Drain current icon toread V(drain)/ld(M1) . This changes one of the axes to read ON resistance. You may have to change the parameter

15、Kp slightly to match the datasheet performance.Switching Time Test JigTo test the switching time of the MOSFET import the model into the LTspice test circuit. Check the datasheet to see how the switching times have been tested. They will be characterised with a certain gate drive voltage, gate drive

16、 resistance and drain voltage and the response time will be characterised when the drain current ramps to a certain level.Run the simulation. Probe the gate voltage. Probe the drain current. Zoom in on the rising edge of the gate/drain waveforms. Left click on the Drain current axis and rescale the

17、axis to measure slightly over the current desired drain current. The timings can now be measured. Rise time is normally measured over 10% to 90% of the desired voltage swing. You may have to change the model capacitances slightly to meet datasheet performance.5. <F5>delete<F6>copy<F7&

18、gt;move component without wires attached<F8>movecomponentswithwiresattached<F9>undoshift<F9> redo<CTRL R>rotates component (once it has been selected using <F7>)<CTRL E>mirrors component (once it has been selected using <F7>)按住ALT鍵，左點擊線，繪制該線上的電流波形。按住ALT鍵，左點擊

19、元件，在組件中顯示瞬時功率。6. LTspice Tutorial 3:生成效率報告為了生成效率報告，選擇 Simulate -> Edit Simulation cmd -> mulating if steady state is detected. 返回至 U 仿真界面，點擊 View -> Efficiency Report -> Show on Schematic. 效率報告就會顯示在原理圖上。(注意：當只有一個電壓源(被認為是輸入)，和或者一個電流源或者負載稱為Rload(假定為負載)，才能生成效率報告。)7. LTspice Tutorial 3:使用數學函

20、數來計算效率|There is no reason why you cannot use the maths functions in LTspice to examine efficiency and indeed this is an effective way of measuring the efficiency of a multi output system.8. 想要知道電路中有哪些寄生參數，可以按<CTRL>+<ALT>+vSHIFT>+H ，原理圖中會以高亮的形式顯示哪些元件有寄生參數，點擊<F9>取消。9. 如何將第三方模型導入 L

21、Tspice?下載SPICE模型，保存到所要仿真的電路的同一路徑里；點擊 SPICE directive，添加以下SPICE指 令.include DI_BAT54.txt,打開SPICE (.txt)模型(in this case it is DI_BAT54)，注意模型的名稱，按 < CTRL >右鍵單擊肖特基二 極管符號和文本 DI_BAT54粘貼到Value字段，如圖1所示。10.結溫終端(Tj)可以用于讀取結溫或固定結溫，這個終端可以浮動；殼溫終端仃c)必須連接到一個電壓源或散熱器RC網絡，該終端不能浮動11. n溝道mosfet安全工作區(SOA)行為建模打開SOAth

22、erm-NMOS Example，啟動原理圖，運行這一仿真，它通過四個步驟加載不同條件下的輸出:1 Q,10 Q,50 Q,100 Q按F2并選擇SOAtherm-NMOS符號。把SOAtherm-NMOS NMOS的符號放到示意圖中， 使用CTRL+R旋轉符號。SOAtherm-NMOS符號作 為覆蓋，NMOS符號不應該被刪除。708Wit.rirflii¥|他呷NTUii2 - xVjIjK.artrr.-E' iveI' n(niTMOi F 口砂 CN：> firt/inrj運行仿真，繪制 Tj-FET結點電壓，該電壓表示結溫（junction temp

23、erature，單位c）,Tj-FET溫度達到了 1 32°C，而起始溫度為85°C的原因是該符號的環境溫度默認為85 C。右鍵單擊符號使Tambient Tambient從85 c變為70 C。打開SOAtherm-NMOS Tutorial 2。運行，會發現現 在的最高結溫Tj-FET是123°CO將MOSFET符號放好之后，額外的電線應該自動刪除。 如果電線沒有自動刪除，手動按下F5,選中，刪除它們。打開 SOAtherm-NMOS Tutorial 1。右鍵單擊（或左鍵雙擊）SOAtherm-NMOS符號，出現SOAtherm-NMOS符號屬性對話框，如下圖所示。右鍵單擊SpiceModel，在下拉菜單中選擇SOAtherm-NMOS模型，本例選擇 PSMN4R8100BSE。如果使用的是 Mac版本的LTspice，可以左擊 使字段可編輯，將MOSFET的名字直接粘貼到 SpiceModel字段。T i*.邛. IRFkSlIMIRFSICIT IRFH53I® iRFIrr5JG£ 怕F牌劃Lb ITQBHHJOP-Sfi-rS 口淫 H-