1、畢業設計(論文)外文資料翻譯學 部： 專 業： 姓 名： 學 號： 外文出處： 附 件：1.外文資料翻譯譯文；2.外文原文。 完成日期： 201 年 月 日 at89c51的概況1 at89c51應用單片機廣泛應用于商業：諸如調制解調器，電動機控制系統，空調控制系統，汽車發動機和其他一些領域。這些單片機的高速處理速度和增強型外圍設備集合使得它們適合于這種高速事件應用場合。然而，這些關鍵應用領域也要求這些單片機高度可靠。健壯的測試環境和用于驗證這些無論在元部件層次還是系統級別的單片機的合適的工具環境保證了高可靠性和低市場風險。intel 平臺工程部門開發了一種面向對象的用于驗證它的at89c51

2、 汽車單片機多線性測試環境。這種環境的目標不僅是為at89c51 汽車單片機提供一種健壯測試環境，而且開發一種能夠容易擴展并重復用來驗證其他幾種將來的單片機。開發的這種環境連接了at89c51。本文討論了這種測試環境的設計和原理，它的和各種硬件、軟件環境部件的交互性，以及如何使用at89c51。1.1 介紹8 位at89c51 chmos 工藝單片機被設計用于處理高速計算和快速輸入/輸出。mcs51 單片機典型的應用是高速事件控制系統。商業應用包括調制解調器，電動機控制系統，打印機，影印機，空調控制系統，磁盤驅動器和醫療設備。汽車工業把mcs51 單片機用于發動機控制系統，懸掛系統和反鎖制動系

3、統。at89c51 尤其很好適用于得益于它的處理速度和增強型片上外圍功能集，諸如：汽車動力控制，車輛動態懸掛，反鎖制動和穩定性控制應用。由于這些決定性應用，市場需要一種可靠的具有低干擾潛伏響應的費用-效能控制器，服務大量時間和事件驅動的在實時應用需要的集成外圍的能力，具有在單一程序包中高出平均處理功率的中央處理器。擁有操作不可預測的設備的經濟和法律風險是很高的。一旦進入市場，尤其任務決定性應用諸如自動駕駛儀或反鎖制動系統，錯誤將是財力上所禁止的。重新設計的費用可以高達500k 美元，如果產品族享有同樣內核或外圍設計缺陷的話，費用會更高。另外，部件的替代品領域是極其昂貴的，因為設備要用來把模塊典

4、型地焊接成一個總體的價值比各個部件高幾倍。為了緩和這些問題，在最壞的環境和電壓條件下對這些單片機進行無論在部件級別還是系統級別上的綜合測試是必需的。intel chandler 平臺工程組提供了各種單片機和處理器的系統驗證。這種系統的驗證處理可以被分解為三個主要部分。系統的類型和應用需求決定了能夠在設備上執行的測試類型。1.2 at89c51提供以下標準功能：4k 字節flash 閃速存儲器，128 字節內部ram，32 個i/o 口線，2 個16 位定時/計數器，一個5 向量兩級中斷結構，一個全雙工串行通信口，片內振蕩器及時鐘電路。同時，at89c51 降至0hz 的靜態邏輯操作，并支持兩種

5、可選的節電工作模式。空閑方式體制cpu 的工作，但允許ram，定時/計數器，串行通信口及中斷系統繼續工作。掉電方式保存ram 中的內容，但振蕩器體制工作并禁止其他所有不見工作直到下一個硬件復位。1.3引腳功能說明vcc：電源電壓gnd：地p0 口：p0 口是一組8 位漏極開路型雙向i/o 口，也即地址/數據總線復用。作為輸出口用時，每位能吸收電流的方式驅動8 個ttl 邏輯門電路，對端口寫“1”可作為高阻抗輸入端用。在訪問外部數據存儲器或程序存儲器時，這組口線分時轉換地址（低8 位）和數據總線復用，在訪問期間激活內部上拉電阻。在flash 編程時，p0 口接受指令字節，而在程序校驗時，輸出指令

6、字節，校驗時，要求外接上拉電阻。p1 口：p1 是一個帶內部上拉電阻的8 位雙向i/o 口，p1 的輸出緩沖級可驅動（吸收或輸出電流）4 個ttl 邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（iil）。flash 編程和程序校驗期間，p1 接受低8 位地址。p2 口：p2 是一個帶有內部上拉電阻的8 位雙向i/o 口，p2 的輸出緩沖級可驅動（吸收或輸出電流）4 個ttl 邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內部存

7、在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（iil）。在訪問外部程序存儲器或16 位四肢的外部數據存儲器（例如執行movx dptr指令）時，p2 口送出高8 位地址數據，在訪問8 位地址的外部數據存儲器（例如執行movx ri 指令）時，p2 口線上的內容（也即特殊功能寄存器（sfr）區中r2 寄存器的內容），在整個訪問期間不改變。flash 編程和程序校驗時，p2 也接收高位地址和其他控制信號。p3 口：p3 是一個帶有內部上拉電阻的8 位雙向i/o 口，p3 的輸出緩沖級可驅動（吸收或輸出電流）4 個ttl 邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作

8、輸入口。作為輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（iil）。p3 口還接收一些用于flash 閃速存儲器編程和程序校驗的控制信號。rst：復位輸入。當振蕩器工作時，rst 引腳出現兩個機器周期以上高電平將使單片機復位。ale/prog：當訪問外部程序存儲器或數據存儲器時，ale（地址鎖存允許）輸出脈沖用于鎖存地址的低8 位字節。即使不訪問外部存儲器，ale 仍以時鐘振蕩頻率的1/6 輸出固定的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是，每當訪問外部數據存儲器時將跳過一個ale 脈沖。對flash 存儲器編程期間，該引腳還用于輸入編程脈沖（p

9、rog）。如有必要，可通過對特殊功能寄存器（sfr）區中的8eh 單元d0 位置位，可禁止ale 操作。該位置位后，只有一條movx 和movc 指令ale 才會被激活。此外，該引腳會被微弱拉高，單片機執行外部程序時，應設置ale 無效。psen：程序存儲允許輸出是外部程序存儲器的讀選通型號，當89c51 由外部存儲器取指令（或數據）時，每個機器周期兩次psen 有效，即輸出兩個脈沖。在此期間，當訪問外部數據存儲器，這兩次有效的psen 信號不出現。ea/vpp：外部訪問允許。欲使cpu 僅訪問外部程序存儲器（地址為0000hffffh），ea 端必須保持低電平（接地）。需注意的是：如果加密位

10、lb1 被編程，復位時內部會鎖存ea 端狀態。如ea 端為高電平（接vcc 端），cpu 則執行內部程序存儲器中的指令。flash 存儲器編程時，該引腳加上+12v 的編程允許電源vpp，當然這必須是該器件使用12v 編程電壓vpp。xtal1：振蕩器反相放大器及內部時鐘發生器的輸入端。xtal2：振蕩器反相放大器的輸出端。89c51 中有一個用于構成內部振蕩器的高增益反相放大器，引腳xtal1 和xtal2分別是該放大器的輸入端和輸出端。這個放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構成自激振蕩器，振蕩電路參見圖5。外接石英晶體或陶瓷諧振器及電容c1、c2 接在放大器的反饋回路中構成

11、并聯振蕩電路。對電容c1、c2 雖沒有十分嚴格的要求，但電容容量的大小會輕微影響振蕩頻率的高低、振蕩器工作的穩定性、起振的難易程度及溫度穩定性，如果使用石英晶體，我們推薦電容使用30pf10 pf，而如使用陶瓷諧振器建議選擇40pf10pf。用戶也可以采用外部時鐘。這種情況下，外部時鐘脈沖接到xtal1 端，即內部時鐘發生器的輸入端xtal2 則懸空。掉電模式：在掉電模式下，振蕩器停止工作，進入掉電模式的指令是最后一條被執行的指令，片內ram 和特殊功能寄存器的內容在終止掉電模式前被凍結。推出掉電模式的唯一方法是硬件復位，復位后將重新定義全部特殊功能寄存器但不改變ram 中的內容，在vcc 恢

12、復到正常工作電平前，復位應無效，且必須保持一定時間以使振蕩器重啟動并穩定工作。89c51 的程序存儲器陣列是采用字節寫入方式編程的，每次寫入一個字符，要對整個芯片的eprom 程序存儲器寫入一個非空字節，必須使用片擦除的方法將整個存儲器的內容清楚。2 編程方法編程前，設置好地址、數據及控制信號，編程單元的地址加在p1 口和p2 口的p2.0p2.3（11 位地址范圍為0000h0fffh），數據從p0口輸入，引腳p2.6、p2.7 和p3.6、p3.7 的電平設置見表6，pseb 為低電平，rst保持高電平，ea/vpp 引腳是編程電源的輸入端，按要求加上編程電壓，ale/prog引腳輸入編程

13、脈沖（負脈沖）。編程時，可采用420mhz 的時鐘振蕩器，89c51 編程方法如下：在地址線上加上要編程單元的地址信號在數據線上加上要寫入的數據字節。激活相應的控制信號。在高電壓編程方式時，將ea/vpp 端加上+12v 編程電壓。每對flash 存儲陣列寫入一個字節或每寫入一個程序加密位，加上一個ale/prog 編程脈沖。改變編程單元的地址和寫入的數據，重復15 步驟，知道全部文件編程結束。每個字節寫入周期是自身定時的，通常約為1.5ms。數據查詢89c51 單片機用數據查詢方式來檢測一個寫周期是否結束，在一個寫周期中，如需要讀取最后寫入的那個字節，則讀出的數據的最高位（p0.7）是原來寫

14、入字節的最高位的反碼。寫周期開始后，可在任意時刻進行數據查詢。2.1ready/busy:字節編程的進度可通過ready/busy 輸出信號檢測，編程期間，ale 變為高電平“h”后p3.4（ready/busy）端被拉低，表示正在編程狀態（忙狀態）。編程完成后，p3.4 變為高電平表示準備就緒狀態。程序校驗：如果加密位lb、lb2 沒有進行編程，則代碼數據可通過地址和數據線讀回原編寫的數據，采用下圖的電路，程序存儲器的地址由p1 口和p2 口的p2.0p2.3 輸入，數據由p0 口讀出，p206、p2.7 和p3.6、p3.7 的控制信號見表6，psen 保持低電平，ale、ea 和rst

15、保持高電平。校驗時，p0 口必須接上10k 左右的上拉電阻。2.2芯片擦除:利用控制信號的正確組合(表6)并保持ale/prog 引腳10ms 的低電平脈沖寬度即可將eprom 陣列(4k 字節)和三個加密位整片擦除,代碼陣列在片擦除操作中將任何非空單元寫入”1”,這步驟需在編程之前進行。2.3讀片內簽名字節:89c51 單片機內有3 個簽名字節,地址為030h、031h 和032h。于聲明該器件的廠商、號和編程電壓。讀簽名字節的過程和單元030h、031h 和032h的正常校驗相仿，只需要將p3.6 和p3.7 保持低電平，返回值意義如下：(030h) = 1eh 聲明產品由atmel 公司

16、制造。(031h) = 51h 聲明為89c51 單片機。(032h) = ffh 聲明為12v 編程電壓。(032h) = 05h 聲明為5 編程電壓。2.4 編程接口：采用控制信號的正確組合可對flash 閃速存儲陣列中的每一代碼字節進行寫入和存儲器的整片擦除，寫操作周期是自身定時的，初始化后它將自動定時到操作完成。微機接口實現兩種信息形式的交換。在計算機之外，由電子系統所處理的信息以一種物理信號形式存在，但在程序中，它是用數字表示的。任一接口的功能都可分為以某種形式進行數據庫變換的一些操作，所以外部和內部形式的轉換是由許多步驟完成的。模擬-數字轉換器（adc）用來將連續變化信號變成相應的

17、數字量，這數字量可是可能性的二進制數值中的一固定值。如果傳感器輸出不是連續變化的，就不需模擬-數字轉換。這種情況下，信號調理單元必須將輸入信號變換成為另一信號，也可直接與接口的下一部分，即微計算機本身的輸入輸出單元相連接。輸出接口采用相似的形式，明顯的差別在于信息流的方向相反；是從程序到外部世界。這種情況下，程序可稱為輸出程序，它監督接口的操作并完成數字-模擬轉換器（dac）所需數字的標定。該子程序依次送出信息給輸出器件，產生相應的電信號，由dac 轉換成模擬形式。最后，信號經調理（通常是放大）以形成適應于執行器操作的形式。在微機電路中使用的信號幾乎總是太小而不能被直接地連到“外部世界”，因而

18、必須用某種形式將其轉換成更適宜的形式。接口電路部分的設計是使用微機的工程師所面臨最重要的任務之一。我們已經了解到微機中，信號以離散的位形式表示。當微機要與只有打開或關閉操作的設備相連時，這種數字形式是最有用的，這里每一位都可表示一開關或執行器的狀態。為了解決實際問題，一個單片機不僅包括cpu，程序和數據存儲器，另外，它必須含有通過cpu 訪問外部信息的硬件。一旦cpu 收集到數據信息和流程，它必須能夠改變外部領域的一部分，這些硬件設備稱作外圍設備，它們是cpu 通往外部的窗口。單片機可利用外圍設備中最基本的用于一般用途的i/o 接口，每個i/o 接口既可作為輸入端又可作為輸出端，每個i/o 接

19、口的功能取決與程序初始化階段對數據方位寄存器相應位進行置一和清零操作，通過cpu 指令對數據寄存器相應位進行置一和清零來置一和清零輸出端口，同樣輸入端口邏輯位也可以通過cpu 指令訪問。一些類型的串行口單元允許cpu 與外部設備進行串口通信，用串口位代替平行位進行通信需要少許的i/o 口，這樣使通信費用降低但速度也相對慢些。串口傳送可以同步也可以異步。the general situation of at89c51chapter 1 the application of at89c51microcontrollers are used in a multitude of commercial

20、applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. the high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. however, these critical applicatio

21、n domains also require that these microcontrollers are highly reliable. the high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. intel platform engin

22、eering department developed an object-oriented multi-threaded test environment for the validation of its at89c51 automotive microcontrollers. the goals of this environment was not only to provide a robust testing environment for the at89c51 automotive microcontrollers, but to develop an environment

23、which can be easily extended and reused for the validation of several other future microcontrollers. the environment was developed in conjunction with microsoft foundation classes (at89c51). the paper describes the design and mechanism of this test environment, its interactions with various hardware

24、/software environmental components, and how to use at89c51.1.1 introductionthe 8-bit at89c51 chmos microcontrollers are designed to handle high-speed calculations and fast input/output operations. mcs 51 microcontrollers are typically used for high-speed event control systems. commercial application

25、s include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. the automotive industry use mcs 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (abs). the at89c51 is espec

26、ially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. because of these critical applications, the market require

27、s a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a cpu with above average processing power in a single package. the financial and legal risk of having

28、 devices that operate unpredictably is very high. once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. redesign costs can run as high as a $500k, much more if the fix means 2 back annotating it acros

29、s a product family that share the same core and/or peripheral design flaw. in addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. to mitigate these problems, it is essential that com

30、prehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. this complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execut

31、e the mission successfully. intel chandler platform engineering group provides post silicon system validation (sv) of various micro-controllers and processors. the system validation process can be broken into three major parts. the type of the device and its application requirements determine which

32、types of testing are performed on the device.1.2 the at89c51 provides the following standard features: 4kbytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. in addi

33、tion, the at89c51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port and interrupt sys -tem to continue functioning. the power-down mode saves the

34、ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1-3pin descriptionvcc supply voltage.gnd ground.port 0：port 0 is an 8-bit open-drain bi-directional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0

35、pins, the pins can be used as high impedance inputs .port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. in this mode p0 has internal pullups. port 0 also receives the code bytes during flash programming, and outputs the

36、 code bytes during program verification. external pullups are required during program verification.port 1：port 1 is an 8-bit bi-directional i/o port with internal pullups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins they are pulled high by the intern

37、al pullups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil) because of the internal pullups. port 1 also receives the low-order address bytes during flash programming and verification.port 2：port 2 is an 8-bit bi-directional i/o port wi

38、th internal pullups. the port 2 output buffers can sink/source four ttl inputs. when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (iil) because of the internal pul

39、lups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to port 2 pins that are externally being pulled low will source current (iil) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program

40、memory and during accesses to external data memory that use 16-bit addresses (movxdptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx ri), port 2 emits the contents of the p2 special function register.

41、port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3：port 3 is an 8-bit bi-directional i/o port with internal pull ups. the port 3 output buffers can sink/source four ttl inputs. when 1s are written to port 3 pins they are pulled

42、high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (iil) because of the pullups.port 3 also serves the functions of various special feature soft the at89c51 as listed below:rst：reset input. a high on this pin for tw

43、o machine cycles while the oscillator is running resets the device.ale/prog：address latch enable output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog) during flash programming. in normal operation ale is emitted at a

44、 constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is

45、active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.psen：program store enable is the read strobe to external program memory. when theat89c51 is executing code from exte

46、rnal program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory.ea/vpp：external access enable. ea must be strapped to gnd in order to enable the device to fetch code from external program memory locations starti

47、ng at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to vcc for internal program executions. this pin all receives the 12-volt programming enable voltage (vpp) during flash programming, for parts that require 12-volt

48、vpp.xtal1：input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2:output from the inverting oscillator amplifier. oscillator characteristicsxtal1 and xtal2 are the input and output, respectively, of an inverting amplifier which can be configured for use a

49、s an on-chip oscillator, as shown in figure 1. either a quarts crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2.there are no requirements on the duty cycle of the external clock si

50、gnal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. idle mode in idle mode, the cpu puts itself to sleep while all the on chip peripherals remain active. the mode is invoked

51、by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. it should be noted that when idle is terminated by a hard ware reset, the device normally resumes pr

52、ogram execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when id

53、le is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. power-down modein the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. the on-chi

54、p ram and special function registers retain their values until the power-down mode is terminated. the only exit from power-down is a hardware reset. reset redefines the sfr but does not change the on-chip ram. the reset should not be activated before vcc is restored to its normal operating level and

55、 must be held active long enough to allow the oscillator to restart and stabilize. the at89c51 code memory array is programmed byte-by byte in either programming mode. to program any nonblank byte in the on-chip flash memory, the entire memory must be erased using the chip erase mode.2 programming a

56、lgorithmbefore programming the at89c51, the address, data and control signals should be set up according to the flash programming mode table and figure 3 and figure 4. to program the at89c51, take the following steps.1. input the desired memory location on the address lines.2. input the appropriate

57、data byte on the data lines. 3. activate the correct combination of control signals. 4. raise ea/vpp to 12v for the high-voltage programming mode. 5. pulse ale/prog once to program a byte in the flash array or the lock bits. the byte-write cycle is self-timed and typically takes no more than 1.5 ms.

58、 repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. data polling: the at89c51 features data polling to indicate the end of a write cycle. during a write cycle, an attempted read of the last byte written will result in the complement of the written datum on po.7. once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. data polling may begin any time after a write cycle has been initiated.