1,現代CMOS工藝基本流程,現代CMOS工藝基本流程,2,SiliconSubstrateP+,2um,725um,SiliconEpiLayerP,選擇襯底,晶圓的選擇摻雜類型（N或P）電阻率（摻雜濃度）晶向高摻雜(P+)的Si晶圓低摻雜(P)的Si外延層,3,SiliconSubstrateP+,SiliconEpiLayerP,PadOxide,熱氧化,熱氧化形成一個SiO2薄層，厚度約20nm高溫，H2O或O2氣氛緩解后續步驟形成的Si3N4對Si襯底造成的應力,4,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Si3N4淀積,Si3N4淀積厚度約250nm化學氣相淀積(CVD)作為后續CMP的停止層,5,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Photoresist,光刻膠成形,光刻膠成形厚度約0.51.0um光刻膠涂敷、曝光和顯影用于隔離淺槽的定義,6,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Photoresist,Si3N4和SiO2刻蝕,Si3N4和SiO2刻蝕基于氟的反應離子刻蝕(RIE),7,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Photoresist,TransistorActiveAreas,IsolationTrenches,隔離淺槽刻蝕,隔離淺槽刻蝕基于氟的反應離子刻蝕(RIE)定義晶體管有源區,8,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,TransistorActiveAreas,IsolationTrenches,除去光刻膠,除去光刻膠氧等離子體去膠，把光刻膠成分氧化為氣體,9,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,FuturePMOSTransistor,SiliconDioxide,FutureNMOSTransistor,Nocurrentcanflowthroughhere!,SiO2淀積,SiO2淀積用氧化物填充隔離淺槽厚度約為0.51.0um，和淺槽深度和幾何形狀有關化學氣相淀積(CVD),10,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,FuturePMOSTransistor,FutureNMOSTransistor,Nocurrentcanflowthroughhere!,化學機械拋光,化學機械拋光(CMP)CMP除去表面的氧化層到Si3N4層為止,11,SiliconSubstrateP+,SiliconEpiLayerP-,FuturePMOSTransistor,FutureNMOSTransistor,除去Si3N4,除去Si3N4熱磷酸(H3PO4)濕法刻蝕，約180,12,TrenchOxide,CrossSection,BareSilicon,平面視圖,完成淺槽隔離(STI),13,SiliconSubstrateP+,SiliconEpiLayerP-,FuturePMOSTransistor,FutureNMOSTransistor,Photoresist,光刻膠成形,光刻膠成形厚度比較厚，用于阻擋離子注入用于N-阱的定義,14,SiliconSubstrateP+,SiliconEpiLayerP-,FutureNMOSTransistor,Photoresist,N-Well,Phosphorous(-)Ions,磷離子注入,磷離子注入高能磷離子注入形成局部N型區域，用于制造PMOS管,15,SiliconSubstrateP+,SiliconEpiLayerP-,FutureNMOSTransistor,N-Well,除去光刻膠,16,Photoresist,SiliconSubstrateP+,SiliconEpiLayerP-,FutureNMOSTransistor,N-Well,光刻膠成形,光刻膠成形厚度比較厚，用于阻擋離子注入用于P-阱的定義,17,SiliconSubstrateP+,SiliconEpiLayerP-,Photoresist,N-Well,Boron(+)Ions,P-Well,硼離子注入高能硼離子注入形成局部P型區域，用于制造NMOS管,硼離子注入,18,SiliconSubstrateP+,SiliconEpiLayerP-,N-Well,P-Well,除去光刻膠,19,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,退火,退火在6001000的H2環境中加熱修復離子注入造成的Si表面晶體損傷注入雜質的電激活同時會造成雜質的進一步擴散快速加熱工藝(RTP)可以減少雜質的擴散,20,TrenchOxide,N-Well,P-Well,CrossSection,完成N-阱和P-阱,平面視圖,21,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,SacrificialOxide,犧牲氧化層生長,犧牲氧化層生長厚度約25nm用來捕獲Si表面的缺陷,22,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,除去犧牲氧化層,除去犧牲氧化層HF溶液濕法刻蝕剩下潔凈的Si表面,23,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,GateOxide,柵氧化層生長,柵氧化層生長工藝中最關鍵的一步厚度210nm要求非常潔凈，厚度精確(1)用作晶體管的柵絕緣層,24,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Polysilicon,多晶硅淀積,多晶硅淀積厚度150300nm化學氣相淀積(CVD),25,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,ChannelLength,Polysilicon,光刻膠成形,光刻膠成形工藝中最關鍵的圖形轉移步驟柵長的精確性是晶體管開關速度的首要決定因素使用最先進的曝光技術深紫外光(DUV)光刻膠厚度比其他步驟薄,26,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,ChannelLength,多晶硅刻蝕,多晶硅刻蝕基于氟的反應離子刻蝕(RIE)必須精確的從光刻膠得到多晶硅的形狀,27,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,GateOxide,PolyGateElectrode,除去光刻膠,28,TrenchOxide,N-Well,P-Well,CrossSection,Polysilicon,平面視圖,完成柵極,29,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,GateOxide,PolyGateElectrode,PolyRe-oxidation,多晶硅氧化,多晶硅氧化在多晶硅表面生長薄氧化層用于緩沖隔離多晶硅和后續步驟形成的Si3N4,30,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,光刻膠成形,光刻膠成形用于控制NMOS管的銜接注入,31,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,Arsenic(-)Ions,NTip,NMOS管銜接注入,NMOS管銜接注入低能量、淺深度、低摻雜的砷離子注入銜接注入用于削弱柵區的熱載流子效應,32,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,NTip,除去光刻膠,33,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,NTip,光刻膠成形,光刻膠成形用于控制PMOS管的銜接注入,34,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,BF2(+)Ions,NTip,PTip,PMOS管銜接注入低能量、淺深度、低摻雜的BF2+離子注入銜接注入用于削弱柵區的熱載流子效應,PMOS管銜接注入,35,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,NTip,PTip,除去光刻膠,36,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,SiliconNitride,ThinnerHere,ThickerHere,NTip,PTip,PTip,Si3N4淀積,Si3N4淀積厚度120180nmCVD,37,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,SpacerSidewall,NTip,PTip,PTip,Si3N4刻蝕,Si3N4刻蝕水平表面的薄層Si3N4被刻蝕，留下隔離側墻側墻精確定位晶體管源區和漏區的離子注入RIE,38,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,NTip,PTip,光刻膠成形,光刻膠成形用于控制NMOS管的源/漏區注入,39,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,Arsenic(-)Ions,N+Drain,N+Source,PTip,NMOS管源/漏注入,NMOS管源/漏注入淺深度、重摻雜的砷離子注入，形成了重摻雜的源/漏區隔離側墻阻擋了柵區附近的注入,40,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,PTip,除去光刻膠,41,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,Photoresist,PTip,光刻膠成形,光刻膠成形用于控制PMOS管的源/漏區注入,42,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,BF2(+)Ions,Photoresist,N+Drain,N+Source,P+Source,P+Drain,PMOS管源/漏注入,PMOS管源/漏注入淺深度、重摻雜的BF2+離子注入，形成了重摻雜的源/漏區隔離側墻阻擋了柵區附近的注入,43,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Source,P+Drain,LightlyDoped“Tips”,除去光刻膠和退火,除去光刻膠和退火用RTP工藝，消除雜質在源/漏區的遷移,44,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,平面視圖,完成晶體管源/漏極，電子器件形成,45,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,除去表面氧化物,除去表面氧化物在HF溶液中快速浸泡，使柵、源、漏區的Si暴露出來,46,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,Titanium,Ti淀積,Ti淀積厚度2040nm濺射工藝Ti淀積在整個晶圓表面,47,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,TitaniumSilicide,UnreactedTitanium,TiSi2形成,TiSi2形成RTP工藝，N2氣氛，800在Ti和Si接觸的區域，形成TiSi2其他區域的Ti沒有變化稱為自對準硅化物工藝(Salicide),48,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,TitaniumSilicide,Ti刻蝕,Ti刻蝕NH4OH+H2O2濕法刻蝕未參加反應的Ti被刻蝕TiSi2保留下來，形成Si和金屬之間的歐姆接觸,49,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,BPSG淀積,硼磷硅玻璃(BPSG)淀積CVD，厚度約1umSiO2并摻雜少量硼和磷改善薄膜的流動性和禁錮污染物的性能這一層絕緣隔離器件和第一層金屬,50,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,BPSG拋光,硼磷硅玻璃(BPSG)拋光CMP在BPSG層上獲得一個光滑的表面,51,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,Photoresist,光刻膠成形,光刻膠成形用于定義接觸孔(Contacts)這是一個關鍵的光刻步驟,52,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,Photoresist,接觸孔刻蝕,接觸孔刻蝕基于氟的RIE獲得垂直的側墻提供金屬和底層器件的連接,53,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,除去光刻膠,54,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,TitaniumNitride,TiN淀積,TiN淀積厚度約20nm濺射工藝有助于后續的鎢層附著在氧化層上,55,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,TitaniumNitride,Tungsten,鎢淀積,鎢淀積CVD厚度不少于接觸孔直徑的一半填充接觸孔,56,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,鎢拋光,鎢拋光CMP除去表面的鎢和TiN留下鎢塞填充接觸孔,57,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,Contact,平面視圖,完成接觸孔，多晶硅上的接觸孔沒有出現在剖面圖上,58,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Ti(200)-electromigrationshunt,TiN(500)-diffusionbarrier,Al-Cu(5000)-mainconductor,TiN(500)-antireflectivecoating,Metal1淀積,第一層金屬淀積(Metal1)實際上由多個不同的層組成濺射工藝,59,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,光刻膠成形,光刻膠成形用于定義Metal1互連,60,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,Metal1刻蝕,Metal1刻蝕基于氯的RIE由于Metal1由多層金屬組成，所以需要多個刻蝕步驟,61,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,除去光刻膠,62,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,Contact,Metal1,平面視圖,完成第一層互連,63,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,IMD淀積,金屬間絕緣體(IMD)淀積未摻雜的SiO2連續的CVD和刻蝕工藝，厚度約1um填充在金屬線之間，提供金屬層之間的絕緣隔離,64,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,IMD拋光,IMD拋光CMP,65,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,Photoresist,光刻膠成形,光刻膠成形用于定義通孔(Vias),66,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,IMD1,通孔刻蝕,通孔刻蝕基于氟的RIE，獲得垂直的側墻提供金屬層之間的連接,67,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,除去光刻膠,68,Tungsten,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,WViaPlug,TiN和鎢淀積,TiN和鎢淀積同第一層互連,69,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,WViaPlug,鎢和TiN拋光,鎢和TiN拋光同第一層互連,70,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,Contact,Metal1,Via1,平面視圖,完成通孔,71,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,WViaPlug,Metal2,Metal2淀積,Metal2淀積類似于Metal1厚度和寬度增加，連接更長的距離，承載更大的電流,72,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,IMD1,WViaPlug,Metal2,光刻膠成形,光刻膠成形相鄰的金屬層連線方向垂直，減小層間的感應耦合,73,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Dra