運(yùn)算器設(shè)計(jì)與實(shí)現(xiàn)

定點(diǎn)數(shù)加/減法部分第四章

(1/3)

運(yùn)算器是計(jì)算機(jī)進(jìn)行算術(shù)運(yùn)算和邏輯運(yùn)算的主要部件，運(yùn)算器的邏輯結(jié)構(gòu)取決于機(jī)器的指令系統(tǒng)、數(shù)據(jù)表示方法和運(yùn)算方法等。本章主要討論數(shù)值數(shù)據(jù)在計(jì)算機(jī)中實(shí)現(xiàn)算術(shù)運(yùn)算和邏輯運(yùn)算的方法，以及運(yùn)算部件的基本結(jié)構(gòu)和工作原理。運(yùn)算器

80486運(yùn)算器簡(jiǎn)化框圖運(yùn)算器內(nèi)部結(jié)構(gòu)運(yùn)算器部分內(nèi)容提要一.定點(diǎn)數(shù)加/減法二.定點(diǎn)數(shù)乘/除法三.定點(diǎn)數(shù)邏輯運(yùn)算四.浮點(diǎn)數(shù)的運(yùn)算--

定點(diǎn)數(shù)加/減法運(yùn)算方法及實(shí)現(xiàn)--定點(diǎn)數(shù)加/減法運(yùn)算中的溢出問題--定點(diǎn)數(shù)乘法算法及實(shí)現(xiàn)--定點(diǎn)數(shù)除法算法及實(shí)現(xiàn)--邏輯運(yùn)算及實(shí)現(xiàn)--位移運(yùn)算及實(shí)現(xiàn)--浮點(diǎn)數(shù)運(yùn)算及實(shí)現(xiàn)運(yùn)算器部分內(nèi)容提要一.定點(diǎn)數(shù)加/減法二.定點(diǎn)數(shù)乘/除法三.定點(diǎn)數(shù)邏輯運(yùn)算四.浮點(diǎn)數(shù)的運(yùn)算--

定點(diǎn)數(shù)加/減法運(yùn)算方法及實(shí)現(xiàn)--定點(diǎn)數(shù)加/減法運(yùn)算中的溢出問題--定點(diǎn)數(shù)乘法算法及實(shí)現(xiàn)--定點(diǎn)數(shù)除法算法及實(shí)現(xiàn)--邏輯運(yùn)算及實(shí)現(xiàn)--位移運(yùn)算及實(shí)現(xiàn)--浮點(diǎn)數(shù)運(yùn)算及實(shí)現(xiàn)一.定點(diǎn)數(shù)加/減法定點(diǎn)數(shù)加/減法運(yùn)算方法原碼加減運(yùn)算對(duì)原碼表示的兩個(gè)數(shù)進(jìn)行加減運(yùn)算時(shí)，符號(hào)位不參與運(yùn)算，僅僅是兩數(shù)的絕對(duì)值參與運(yùn)算。計(jì)算機(jī)的實(shí)際操作是加還是減，不僅取決于指令的操作碼，還取決于兩個(gè)操作數(shù)的符號(hào)，例如：加法時(shí)可能要做減法（兩數(shù)異號(hào)）；減法時(shí)又可能做加法（兩數(shù)異號(hào)），所以原碼加減運(yùn)算的實(shí)現(xiàn)是比較復(fù)雜的。補(bǔ)碼加減運(yùn)算1.補(bǔ)碼加法兩個(gè)補(bǔ)碼表示的數(shù)相加，符號(hào)位參加運(yùn)算，且兩數(shù)和的補(bǔ)碼等于兩數(shù)補(bǔ)碼之和，即

[X+Y]補(bǔ)=[X]補(bǔ)+[Y]補(bǔ)2.補(bǔ)碼減法根據(jù)補(bǔ)碼加法公式可推出：

[X-Y]補(bǔ)=[X+(-Y)]補(bǔ)=[X]補(bǔ)+[-Y]補(bǔ)已知[Y]補(bǔ)求[-Y]補(bǔ)的方法是：將[Y]補(bǔ)連同符號(hào)位一起求反，末尾加“1”。

[-Y]補(bǔ)被稱為[Y]補(bǔ)的機(jī)器負(fù)數(shù)，由[Y]補(bǔ)求[-Y]補(bǔ)的過程稱為對(duì)[Y]補(bǔ)變補(bǔ)（求補(bǔ)），表示為：

[-Y]補(bǔ)=[[Y]補(bǔ)]變補(bǔ)

我們要注意將“某數(shù)的補(bǔ)碼表示”與“變補(bǔ)”這兩個(gè)概念區(qū)分開來。一個(gè)負(fù)數(shù)由原碼表示轉(zhuǎn)換成補(bǔ)碼表示時(shí)，符號(hào)位是不變的，僅對(duì)數(shù)值位的各位變反，末尾加“1”。而變補(bǔ)則不論這個(gè)數(shù)的真值是正是負(fù)，一律連同符號(hào)位一起變反，末尾加“1”。

[Y]補(bǔ)表示的真值如果是正數(shù)，則變補(bǔ)后[-Y]補(bǔ)所表示真值變?yōu)樨?fù)數(shù)，反之亦然。定點(diǎn)數(shù)加/減法運(yùn)算方法

［+1］補(bǔ)=0001［+1］補(bǔ)=0001+［+３］補(bǔ)=0011+［-3］補(bǔ)=1101

［+４］補(bǔ)=0100［-2］補(bǔ)=1110

［-1］補(bǔ)=1111+［+2］補(bǔ)=0010

［+1］補(bǔ)=10001Addition/SubtractionofTwosComplement

Carry-outisignoredInadd/suboftwo’scomplementsignbitcanbehandledasmagnitudebit

1+3=4

1-3=-2

-1+2=11-bitALUDesign

32-bitALUDesignOverflowDetectionLogicHowtoperformSubtractionontheALUCarrylookaheadlogicMenuofthetopic定點(diǎn)數(shù)加/減法實(shí)現(xiàn)電路

1.ANDgateABOut000010100111ABOut000011101111OutABABOutABOut0000111011104.XORgate(half-adder)AAOut1001OutABOut=A×BOut=A＋BOut=AOut=A＋

B2.ORgate3.InverterBasicLogicalUnit（1）5.MutiplexerABdout01dout01ABIFd==0out=AElseout=BABdoutBasicLogicalUnit（2）D103S1out....12S0D0D2D3數(shù)據(jù)選擇控制輸入S1S0選中的數(shù)據(jù)輸出out00011011D0D1D2D30

0

0

01

1

1

0

D1BasicLogicalUnit（3）4:1MutiplexerThe1-bitlogicalunitforANDandORPerformsANDandOR1）Operation=0，選擇OR輸出2）Operation=1，選擇AND輸出(0)0000(0)00(0)(0)001111100111(0)(0)(0)(1)(1)(1)(1)(carry)+......Additionfor1-bitunitTherearethreeinputs(twooperandsandonecarry-in)twooutputs(sumandcarry-out)For1-bitadder:outputinputTruthtableforinput/outputAdditionfor1-bitunitTurntruthtableintoalogicalequation:◆

CarryOut=(b&CarryIn)∣(a&CarryIn)∣(a&b)∣(a&b&CarryIn)Simplifytheequationto：CarryOut=(b&CarryIn)∣(a&CarryIn)∣(a&b)◆

Sum=(a&b&CarryIn)∣(a&b&CarryIn)∣Sum=aXORbXORCarryIn(a&b&CarryIn)∣(a&b&CarryIn)

Additionfor1-bitunitSimplifytheequationto：Additionfor1-bitunit1-bitfulladderabCarryIn●●●●CarryOutresultabCarryOutCarryInOperation210OperationresultCarryInCarryOutALUPerformsAND,ORandaddition（完成1位“與”、“或”、“加”運(yùn)算）andoradd1-bitFullAdder

1-bitALU221）Operation=0，選擇AND輸出2）Operation=1，選擇OR輸出3）Operation=2，選擇Add輸出a0CarryInresult0Operationresult1CarryInALU0CarryOutCarryInCarryInCarryInCarryOutCarryOutCarryOutALU1ALU2ALU31b0result2result31a1a2a31b1b2b31……Addition(注意):作為加法器時(shí)第一個(gè)進(jìn)位輸入為0CarryIn[0]=0A32-bitALUconstructedfrom321-bitALUsusuallyinterestedincalculationmorethantwobitsthismotivatestheneedfortheCascadedMulti-bitALU21）Operation=0，選擇32bitAND輸出2）Operation=1，選擇32bitOR輸出3）Operation=2，選擇32bitAdd輸出b0b1b2…b31a0a1a2…a31CarryOut32-bitALU(32位算術(shù)邏輯單元)

［+1］補(bǔ)=0001［+1］補(bǔ)=0001+［+３］補(bǔ)=0011+［-3］補(bǔ)=1101

［+４］補(bǔ)=0100［-2］補(bǔ)=1110

［-1］補(bǔ)=1111+［+2］補(bǔ)=0010

［+1］補(bǔ)=10001Addition/SubtractionofTwosComplement

Carry-outisignoredInadd/suboftwo’scomplementsignbitcanbehandledasmagnitudebit

1+3=4

1-3=-2

-1+2=1?

溢出問題概述

溢出的檢測(cè)方法Menuofthetopic定點(diǎn)數(shù)加/減法運(yùn)算中的溢出問題

7+3=10but... -4-5=-9but...01110011+1010111001011+0111110731–6–4–57Overflow:Whenaddingoperandswithsamesigns,theresultisdifferentExamples:

溢出問題概述5+3=-8!-7-2=+7!0000000100100011100001010110010010011010101111001101011111101111+0+1+2+3+4+5+6+7-8-7-6-5-4-3-2-10000000100100011100001010110010010011010101111001101011111101111+0+1+2+3+4+5+6+7-8-7-6-5-4-3-2-1ReasonofOverflowtheresultistoolarge(ortoosmall)torepresentproperlyOverflowConditionsOverflow:theresultistoolarge(ortoosmall)torepresentproperlyExample:rangeof4-bitbinarynumber（signed）

[-8,+7]Whenaddingoperandswithdifferentsigns,overflowcannotoccur!Overflowoccurswhenadding:2positivenumbersandthesumisnegative2negativenumbersandthesumispositiveOnyourown:Proveyoucandetectoverflowby:CarryintoMSBandCarryoutofMSB

CarryintoMSBCarryoutofMSB=1OverflowwhencarryintosigndoesnotequalcarryoutMethod1

（最高進(jìn)位和次高進(jìn)位法）當(dāng)向符號(hào)位的進(jìn)位（由次高位產(chǎn)生）不等于符號(hào)位產(chǎn)生的進(jìn)位（由符號(hào)位產(chǎn)生）則發(fā)生溢出

溢出的檢測(cè)方法Overflowwhencarryintosigndoesnotequalcarryout01110011+1010111001011+011111010Examplesoverflow73-6+-4-57+overflow01010010+01110000Nooverflow527+11011011+10001111Nooverflow-3-5-8+1Carry-outisignoredCarryInCarryInCarryOutCarryOutALU31ALU30…result31result30CarryIn29CarryIn31CarryIn30a31a30b31b30OverflowXYXXORY000011101110

CarryintoMSB&CarryoutofMSBForaN-bitALU:Overflow=CarryIn[N-1]XORCarryOut[N-1]Method1

（最高進(jìn)位和次高進(jìn)位法）OverflowDetectionLogic(溢出檢測(cè)邏輯)[x]雙補(bǔ)

=

x1＞x≥0２２+x0＞x≥–1（mod4）[x]雙補(bǔ)=

0，x2n

＞x≥02n+２

+x0＞x≥2n（mod2n+２）[A]補(bǔ)=０0.1010[A]補(bǔ)=１1.0001

[B]補(bǔ)=０0.1001

[A

+

B]補(bǔ)=

０

1.0011

[B]補(bǔ)=１1.0101

[A

+

B]補(bǔ)=

１

0.0110UsingDoublesignsTwosComplementinoverflowdetectionMethod2:雙符號(hào)位法

溢出的檢測(cè)方法00,×××××11,×××××10,×××××01,×××××whentwosignbitsoftheresultaresamethereisnooverflowsumisnegativesumispositivewhentwosignbitsoftheresultaredifferentthereisoverflow

NegativeoverflowPositiveoverflowMSBisthesignoftheresult

溢出的檢測(cè)方法CarryInCarryInCarryOutCarryOutALU31ALU30…result31(符號(hào)位)result30(符號(hào)位)CarryIn29CarryIn31CarryIn30a31a30b31b30OverflowMethod2:雙符號(hào)位法UsingDoublesignsTwosComplementinoverflowdetectionwhentwosignbitsoftheresultaredifferentthereisoverflow

whentwosignbitsoftheresultaresamethereisnooverflow

Overflow=1，溢出；

0，沒有溢出注：最高兩位是符號(hào)位OverflowDetectionLogic(溢出檢測(cè)邏輯)A-B=A+(–B)=A+B+1formtwocomplementbyinvertandaddoneSoweonlyneedadditionandcomplementcircuits

Taketwoscomplimentofsubtrahendandaddtominuend-i.e.a-b=a+(-b)HowtoperformSubtractionontheALUweconstructedbefore?abCarryInCarryOutresultabCarryOutCarryIn＋Operation210OperationresultCarryInCarryOutALU01BinvertBinvertHowtoperformSubtractionontheALU

weconstructedbefore?WhenBinvert=1

inputsoffulladderareaandb

已有全加器加入輸入為Ba0CarryIn=1result0Operationresult1CarryInALU0CarryOutCarryInCarryInCarryInCarryOutCarryOutCarryOutALU1ALU2ALU31b0result2result31a1a2a31b1b2b31……Binvert=1CarryIn=1Binvert=1Subtractionon32-bitALUForSubtractionA-B=A+(-B)=A+B+1a0CarryInresult0Operationresult1CarryInALU0CarryOutCarryInCarryInCarryInCarryOutCarryOutCarryOutALU1ALU2ALU31b0result2result31a1a2a31b1b2b31……CarryIn=0BinvertCarryIn=1Binvert=1Binvert=0Addition/Subtractionon32-bitALUForadditionForSubtraction

SoweonlyneedadditionandcomplementcircuitsA-B=A+(-B)=A+B+1a0CarryInresult0Operationresult1CarryInALU0CarryOutCarryInCarryInCarryInCarryOutCarryOutCarryOutALU1ALU2ALU31b0result2result31a1a2a31b1b2b31……lesslesslessless…SetoverflowBnegate=1Bnegate=0ForadditionForSubtractionBnegateCombiningtheBinvertandCarryIntoBnegatea0CarryInresult0Operationresult1CarryInALU0CarryOutCarryInCarryInCarryInCarryOutCarryOutCarryOutALU1ALU2ALU31b0result2result31a1a2a31b1b2b31……lesslesslessless…SetoverflowBnegateAddsaZerodetector…ZeroBinvert=1(A-B)Zero=1A=BZero=0A≠BControlsignsandcorrespondingoperationThevaluesofthethreeALUcontrollinesBnegate(1-bit)Andoperation(2-bit)andcorrespondingoperationsUniversalsymbolforacompleteALUThesymbolisalsotorepresentanadder,soitisnormallylabeledeitherwithALUorAdder

設(shè)計(jì)一個(gè)1位ALU,完成一位加法、AND、OR和NOT操作。輸入為A、B，輸出為z。當(dāng)加法運(yùn)算時(shí)，有進(jìn)位輸出CarryOut;當(dāng)AND、OR和NOT操作時(shí)，CarryOut為O。在下圖上通過連線完成上述設(shè)計(jì)（注：不能添加任何其他部件）。例:00011011全加器數(shù)據(jù)輸入F0F1abCarryInCarryOut輸出F0F1

功能00

ADD（A，B）01

AND（A，B）10

OR（A，B）11

NOT（A）CarryOut輸出CarryIn數(shù)據(jù)輸入2:4譯碼器Z例(cont)00011011全加器數(shù)據(jù)輸入F0F1abCarryInCarryOut輸出F0F1

功能00

ADD（A，B）解:

ADD（A，B）00011011全加器數(shù)據(jù)輸入F0F1abCarryInCarryOut輸出F0F1

功能01

AND（A，B）

AND（A，B）00011011全加器數(shù)據(jù)輸入F0F1abCarryInCarryOut輸出F0F1

功能10

OR（A，B）OR（A，B）00011011全加器數(shù)據(jù)輸入F0F1abCarryInCarryOut輸出F0F1

功能11

NOT（A）NOT（A）00011011全加器數(shù)據(jù)輸入F0F1abCarryInCarryOut輸出功能實(shí)現(xiàn)邏輯圖RippleCarryCriticaldelay:thepropagationofcarryfromlowtohighorderstagesCO

A14

B14

A1B1A0B0S15S14S1S0C-11-bitFullAdderB15A15

1-bitFullAdder1-bitFullAdder1-bitFullAdder….C15C1C1416stageadderfinalsumAndcarryCarrylookaheadlogictwogatedelaystocomputeCOlatearrivingsignal2delaystocomputesumbutlastcarrynotreadyuntil30delayslaterT0:InputstotheadderarevalidT2:Stage0carryout(C0)T4:Stage1carryout(C1)T30:Stage14carryout(C14)T32:Stage15carryout(C15)RippleCarry…AfastaddercircuitmustspeedupthegenerationofthecarrysignalsCriticaldelay:thepropagationofcarryfromlowtohighorderstagesCi=Ai●Bi

＋(AiBi)Ci-1

Ci

=Gi＋Pi●Ci-1Gi=Ai●BiPi=AiBiCi-1carryinforstagei(fromstagei-1)Cicarryoutforstagei(tostagei+1)AnalysisofCarryThelogicexpressionsforsi(sum)ansci(carry-out)ofstageiare:Wecanwrite:

Where:CarryGenerateforstageimustgeneratecarrywhenA=B=1CarryPropagateforstageiCarryoutwillequalcarryinhereForstagei,outputcarryCiindependentoninputcarryCi–1Wecanre-expressedcarryintermsofgenerate/propagate:Onlydependentonstage0carryC–1

C0=G0＋P0C-1

C1

=G1＋P1C0

=G1＋P1(G0＋P0C-1)=G1＋P1G0＋P1P0C-1

C2

=G2＋P2C1=G2＋P2G1＋P2P1G0＋P2P1P0C-1

C3=G3＋P3C2=G3＋P3G2＋P3P2G1＋P3P2P1G0＋P3P2P1P0

C-1…

C15

=G15＋P15C14=G15＋P15G14＋P15P14G13＋P15P14P13G12＋P15P14P13P12G11

＋…＋P15P14P13P12P11P10P9P8P8P7P6P5P4P3P2P1P0C-1AnalysisofCarryPlumbingasCarryLookaheadAnalogy

C0=G0＋P0C-1

C1

=G1＋P1C0

=G1＋P1(G0＋P0C-1)=G1＋P1G0＋P1P0C-1

C2

=G2＋P2C1=G2＋P2G1＋P2P1G0＋P2P1P0C-1

C3=G3＋P3C2=G3＋P3G2＋P3P2G1＋P3P2P1G0＋P3P2P1P0

C-14bitadderswithinternalcarrylookaheadEachofthecarryequationscanbeimplementedinatwo-levellogicnetworkVariablesaretheadderinputsandcarryintostage0!Re-expressthecarrylogicasfollows:CarryLookaheadImplementationAdderwithPropagateandGenerateOutputsIncreasinglycomplexlogic

4bitadderswithripplecarry

4bitadderswithcarrylookahead×××

4bitadderswithcarrylookahead4bitadderswithinternalcarrylookaheadConstructingfastadder-1Method1Using4bitadderswithinternalcarrylookaheadasagroup,CascadedMulti-groupAdderbyripplecarrybetweengroups

16-bitadderbuiltfrom4-bitcarrylookaheadadderbymethod1sumscomputedmuchfasterTimingdiagramofCascadedMulti-groupAdderbyripplecarrybetweengroups

Constructingfastadder-1Constructingfastadder-2Method2Using4bitadderswithinternalcarrylookaheadasagroup,CombiningMulti-groupAdderbyusingsecondlevelcarrylookaheadunit,extendscarrylookaheadforgroups4bitadderswithinternalcarrylookaheadsecondlevelcarrylookaheadunit,extendslookaheadto16bitsGroupP=P3P2P1P0GroupG=G3+P3G2+P3P2G1+P3P2P1G0AnalysisofCarryforgroupsCarryofeachgroup:C3C7

C11

C15Thelogicexpressionfor

C3

C3=G3＋P3G2＋P3P2G1＋P3P2P1G0＋P3P2P1P0

C-1=G3*

＋P3*

C-1G3*

=G3＋P3G2＋P3P2G1＋P3P2P1G0P3*

=P3P2P1P0where：gruop1

C3C7C11C15C-1A0-3A7-4A11-8A15-12B15-12B11-8S11-8B7-4S7-4B0-3S0-3S15-12AnalysisofCarryforgroupsCarryGenerateforgroup1CarryPropagateforgroup1gruop2

gruop4

gruop4

Dividing16bitaddersinto4groups,eachgroup4bitsWithinternalcarrylookahead2ndlevelCarry,PropagateasPlumbing

C3=G3*

＋P3*

C-1

C7

=G7*

＋P7*

C3

=G7*

＋P7*

G3*

＋P7*P3*

C-1

C11

=G11*

＋P11*

C7*=G11*

＋P11*

G7*

＋P11*

P7*

G3*

＋P11*

P7*

P3*

C-1

C15=G15*

＋P15*

C11

=G15*

＋P15*

G11*

＋P15*

P11*

G7*

＋P15*

P11*

P7*

G3*

＋P15*

P11*

P7*

P3*

C-1Carryofeachgroup

C3，C7

，C11

，C15

：AnalysisofCarryforgroupsG7*

=G7＋P7G6＋P7P6G5＋P7P6P5G4

P7*

=P7P6P5P4G11*

=G11＋P11G10＋P11P10G9＋P11P10P9G8P11*

=P11P10P9P8P15*

=P15P14P13P