PAGEPAGE6北華航天工業(yè)學(xué)院《EDA技術(shù)綜合設(shè)計(jì)》課程設(shè)計(jì)報(bào)告報(bào)告題目：數(shù)字秒表設(shè)計(jì)作者所在系部：電子工程系作者所在專業(yè)：自動化作者所在班級：B08221作者姓名：李龍指導(dǎo)教師姓名：崔瑞雪完成時間：2010/12/3內(nèi)容摘要秒表共有6個輸出顯示，分別為百分之一秒、十分之一秒、秒、十秒、分、十分，所以共有6個計(jì)數(shù)器與之相對應(yīng)，6個計(jì)數(shù)器的輸出全都為BCD碼輸出，這樣便于和顯示譯碼器的連接。當(dāng)計(jì)時達(dá)60分鐘后，蜂鳴器鳴響10聲。除此之外，整個秒表還需有一個啟動信號和一個歸零信號，以便秒表能隨意停止及啟動。秒表的邏輯結(jié)構(gòu)較簡單，它主要由顯示譯碼器、分頻器、十進(jìn)制計(jì)數(shù)器、六進(jìn)制計(jì)數(shù)器和報(bào)警器組成。四個10進(jìn)制計(jì)數(shù)器：用來分別對百分之一秒、十分之一秒、秒和分進(jìn)行計(jì)數(shù)；兩個6進(jìn)制計(jì)數(shù)器：用來分別對十秒和十分進(jìn)行計(jì)數(shù)；分頻器：用來產(chǎn)生100HZ計(jì)時脈沖；顯示譯碼器：完成對顯示的控制。根據(jù)電路持點(diǎn)，用層次設(shè)計(jì)概念將此設(shè)計(jì)任務(wù)分成若干模塊，規(guī)定每一模塊的功能和各模塊之間的接口。。按適配劃分后的管腳定位，同相關(guān)功能塊硬件電路接口連線。用VHDL語言描述所有底層模塊。清零信號為異步清零。當(dāng)最高位記到6時停止計(jì)數(shù)顯示譯碼器全部顯示零，并發(fā)出十聲警報(bào)聲。按下復(fù)位按鈕后繼續(xù)計(jì)數(shù)。關(guān)鍵詞：秒表、計(jì)數(shù)器、蜂鳴器、顯示器

目錄十進(jìn)制計(jì)數(shù)器?????????????????????????????????????????????????????5六進(jìn)制計(jì)數(shù)器?????????????????????????????????????????????????????6選擇數(shù)碼管????????????????????????????????????????????????????????8顯示數(shù)碼管????????????????????????????????????????????????????????9響鈴裝置????????????????????????????????????????????????????????????10總設(shè)計(jì)電路圖?????????????????????????????????????????????????????11實(shí)驗(yàn)總結(jié)????????????????????????????????????????????????????????????12參考文獻(xiàn)????????????????????????????????????????????????????????????12課題名稱數(shù)字秒表設(shè)計(jì)完成時間2指導(dǎo)教師崔瑞雪職稱副教授學(xué)生姓名李龍班級B08221總體設(shè)計(jì)要求和技術(shù)要點(diǎn)秒表共有6個輸出顯示，分別為百分之一秒、十分之一秒、秒、十秒、分、十分，所以共有6個計(jì)數(shù)器與之相對應(yīng)，6個計(jì)數(shù)器的輸出全都為BCD碼輸出，這樣便于和顯示譯碼器的連接。當(dāng)計(jì)時達(dá)60分鐘后，蜂鳴器鳴響10聲。除此之外，整個秒表還需有一個啟動信號和一個歸零信號，以便秒表能隨意停止及啟動。秒表的邏輯結(jié)構(gòu)較簡單，它主要由顯示譯碼器、分頻器、十進(jìn)制計(jì)數(shù)器、六進(jìn)制計(jì)數(shù)器和報(bào)警器組成。在整個秒表中最關(guān)鍵的是如何獲得一個精確的100HZ計(jì)時脈沖。工作內(nèi)容及時間進(jìn)度安排周一器件的熟悉及連接，調(diào)試程序的可運(yùn)行性。周二秒表的運(yùn)行及驗(yàn)收。課程設(shè)計(jì)成果1．與設(shè)計(jì)內(nèi)容對應(yīng)的軟件程序2．課程設(shè)計(jì)報(bào)告書3．成果使用說明書4．設(shè)計(jì)工作量要求課程設(shè)計(jì)任務(wù)書十進(jìn)制計(jì)數(shù)器模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycount10isport(clr,start,clk:instd_logic;cout:outstd_logic;daout:bufferstd_logic_vector(3downto0));endcount10;architecturebehaveofcount10isbeginprocess(clr,start,clk)beginifclr='1'thendaout<="0000";elsif(clk'eventandclk='1')thenifstart='1'thenifdaout="1001"thendaout<="0000";cout<='1';elsedaout<=daout+1;cout<='0';endif;endif;endif;endprocess;endbehave;六進(jìn)制計(jì)數(shù)器模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycount6isport(clr,start,clk:instd_logic;cout:outstd_logic;daout:bufferstd_logic_vector(3downto0));endcount6;architecturebehaveofcount6isbeginprocess(clr,start,clk)beginifclr='1'thendaout<="0000";elsif(clk'eventandclk='1')thenifstart='1'thenifdaout="0101"thendaout<="0000";cout<='1';elsedaout<=daout+1;cout<='0';endif;endif;endif;endprocess;endbehave;六進(jìn)制計(jì)數(shù)器模塊（當(dāng)最高位為六時清零）libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycount6_2isport(clk,start,clr:instd_logic;cout:outstd_logic;daout:outstd_logic_vector(3downto0));endcount6_2;architecturetwoofcount6_2issignalq0:std_logic_vector(3downto0);signalq1:std_logic;beginprocess(clk,clr)beginifclr='1'thenq0<="0000";q1<='0';elsifclk'eventandclk='1'thenifstart='1'thenifq0="0101"thenq0<="0000";q1<='1';elseq0<=q0+1;q1<='0';endif;endif;endif;endprocess;daout<=q0;cout<=q1;end;選擇模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityseltimeisport(clr,clk:instd_logic;dain1:instd_logic_vector(3downto0);dain2:instd_logic_vector(3downto0);dain3:instd_logic_vector(3downto0);dain4:instd_logic_vector(3downto0);dain5:instd_logic_vector(3downto0);dain6:instd_logic_vector(3downto0);sel:outstd_logic_vector(2downto0);daout:outstd_logic_vector(3downto0));endseltime;architecturebehaveofseltimeissignalcount:std_logic_vector(2downto0);beginsel<=count;process(clr,clk)beginifclr='1'thencount<="000";elsif(clk'eventandclk='1')thenifcount="110"thencount<="000";elsecount<=count+1;endif;endif;casecountiswhen"001"=>daout<=dain1;when"010"=>daout<=dain2;when"011"=>daout<=dain3;when"100"=>daout<=dain4;when"101"=>daout<=dain5;when"110"=>daout<=dain6;whenothers=>null;endcase;endprocess;endbehave;數(shù)碼管顯示模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitydeledisport(num:instd_logic_vector(3downto0);led:outstd_logic_vector(6downto0));enddeled;architecturebehaveofdeledisbeginprocess(num)--abcdefgbegincasenumiswhen"0000"=>led<="1111110";when"0001"=>led<="0110000";when"0010"=>led<="1101101";when"0011"=>led<="1111001";when"0100"=>led<="0110011";when"0101"=>led<="1011011";when"0110"=>led<="1011111";when"0111"=>led<="1110000";when"1000"=>led<="1111111";when"1001"=>led<="1111101";whenothers=>null;endcase;endprocess;endbehave;Alarm模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityalarmisport(clk,i:instd_logic;q:outstd_logic);endalarm;architecturebehaveofalarmissignalcount:integerrange0to20;signalq0:std_logic;beginprocess(clk,i)beginif(clk'eventandclk='1')thenifi='0'thencount<=0;q0<='0';elsifi='1'thenifcount<=19thencount<=count+1;q0<=notq0;endif;endif;endif;endprocess;q<=q0;endbehave;實(shí)驗(yàn)總結(jié)這次課程設(shè)計(jì)歷時兩天，通過這次的學(xué)習(xí)，發(fā)現(xiàn)了自己的很多不足（你的不足之一就是欠認(rèn)真，請重寫報(bào)告，其他不足我還未發(fā)現(xiàn)，若有，自己偷著改吧），自己知識的很多漏洞，看到了自己的實(shí)踐經(jīng)驗(yàn)還是比較缺乏，理論聯(lián)系實(shí)際的能力還需要提高。通過這次學(xué)習(xí)，我不僅學(xué)會了使用Max+plusⅡ軟件進(jìn)行仿真，進(jìn)一步學(xué)會了EDA的理論知識。這次課程設(shè)計(jì)讓我理解到理論與實(shí)際