UsingAdvancedDesignSystemtoDesignanMMICAmplifier

ApplicationNoteNumber1462

AgilentEEsofEDA

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Contents

Introduction 3

Two-StageMMICAmplifierDesign 5

Branch-LineCouplerDesign 16

Conclusion 29

Appendixes

AppendixA–UsingtheAdvancedModelComposer

toCreateaLibraryofInductorModels 30

AppendixB–RunningtheDesignRuleChecker 37

GeneralReferencesonBalancedAmplifiers

"MicrowavesandRFCircuits:Analysis,Synthesi,s"MaxW.Medley,ArtechHouse,1993,pp509-541.

"FoundationsforMicrostripCirc,u"itDesign

T.C.Edwards,JohnWileyandSons,1981,pp.242-244.

andDesigns

Introduction

TherearemanydesignstepsrequiredforthedevelopmentandmanufactureofMMICcircuits,asillustratedintheMMICDesignFlow.AdvancedDesignSystem(ADS)isacentralpartofthecompleteMMICdesignflow,andisusedthroughoutthisprocess.Thisapplicationnoteillustrates,throughthedesignofanMMICamplifier,severalofthecommonproblemsfacedindesigning,simulating,andproducingaphysicallayoutofanMMICcircuit,aswellasthevalidationstepsthatareneededtoverifythatthephysicallayoutstillproducesthedesiredresult.ItisbeyondthescopeofthisnotetodescribeallpossibledesignspecificationsforanMMICcircuit,butitdoesincludeenoughspecificationanddesignstepstoaddressmanycommondesignchallenges.

Thefollowingsectionsgiveastep-bystepdescriptionofa0.5-Watt,10-GHz,narrow-bandamplifierona100-μmGaAssubstrate.Theexamplefilesthatareusedhere($HPEESOF_DIR/examples/MW_Ckts/MMIC_Amp_prjandMMIC_AmpEM_Sims_prj)

areincludedwiththeADS2003Asoftware.Designanddatadisplayfilenamesfromtheexamplesarereferencedthroughout.

TheseexampledesignsusecomponentsfromagenericdesignkitthatisprovidedwithADS2003A($HPEESOF_DIR/examples/DesignKit/DemoKit.)Themodelsforthesecomponentsdonotcorrespondtoanyspecificfoundryprocess,butarerepresentativeofdesignkitsavailablefrommanyfoundries.

Althoughthedevelopmentofthegenericdesignkitisoutsidethescopeofthisapplicationnote,itisdocumentedintheADS2003Amanual,titledDesignKitDevelopment.Thismanualprovidesinstructionsthatguidefoundriesindevelopingtheirowndesignkits.

Theamplifierdesignprocessdependsonanumberoffactors,includingdesired

specifications,availabilityofdevicemodels,designerpreference,andmore.Thisappli-cationnotedescribesoneofmanypotentialsequences.Weassumethattwostagesofamplificationwillberequired:anoutputstageforpowerandaninputstagetoattainsufficientgain.Thedesignisabalancedamplifier,consistingoftwoparallel,two-stageamplifiers,withbranch-linecouplersattheinputandoutputimplementedaslumpedelementequivalentcircuits,tosplitthesignalattheinputandrecombineitat

theoutputafteramplification.

Figure1showsablockdiagramofthebalancedamplifiertopology.Figure2outlineshowtheimpedancestopresenttothedeviceswerechosen.

Thedesignflowbeginswithseveralsimulationstepsandproceedswithphysicaldesignsteps,withsomesimulationsforverificationofthephysicaldesign.Threemaindesigntasksarerequiredtocompletetheamplifier:designofthefirst-stage(preamplifier),designofthesecondstage(poweramplifier),anddesignofthe

branch-linecouplers.

1_0

Input

0.707_0

3-dB

coupler

3-dB

coupler

0.707_90

Output

Inputmatching

1stFETwith

stabilization

Interstagematching

2nd Output

FET matching

Figure1.Balancedamplifierblockdiagram,utilizingtwo,two-stageamplifiersinparallel.

(a)

(d)

1stFETwith

stabilization

2ndFET

(b)

(c)

Figure2.Choosingimpedances.(a)ChoosesourceZforminimumnoisefigure,aslongasgainremainsreasonable.(b)ChooseloadZforconjugatematching,afterchoosingsourceZ(althoughaslightmismatchwasfoundtogiveahigher1-dBgaincompressionoutputpower).(c)ChoosesourceZforconjugatematching,afterchoosingloadZ.(d)ChooseloadZformaximumpowerdelivered.

Two-StageMMICAmplifierDesign

Thissectionoutlinesthegeneralstepsfortwo-stageMMICamplifierdesign.

Selectanactivedevice.

Thiswilldependonthespecificationsyouareattemptingtomeet(suchasfrequency,power,andnoise),andthedevicesofferedbyaparticularfoundry.TheDemoKithasonlyonedevice,aHEMT(highelectronmobilitytransistor),soaselectionprocessisnotrequired.

Idealbias–first-stage

Chooseabiaspointtomaximizethetransconductance,Gm,whichshouldalsomaximizethegainofthefirst-stagedevice.TheFET_Gm_Calcsschematic,showninFigure3,simulatestheI-VcurvesofthedeviceandcalculatesGmateachbiaspointasafunctionoftheslopeoftheIDS-versus-VGScurve.

TheplotinFigure4indicatesthatbiasingVGStoabout–0.15VshouldmaximizeGm.TheAmplifierDesignGuidehasanupdatedversionofthissimulationsetup,underDesignGuide>Amplifier>DCandBiasPointSimulations>FETI-VCurves,ClassAPower,Eff.,Load,Gmvs.Bias,thatcalculatesGmversusDCbiaspoint,usinganACsimulationatonefrequencytodetermineGm.

Figure3.TheFET_Gm_Calcsschematic,forsimulatingadevice’stransconductanceversusbias.

Figure4.Plotofdraincurrent,IDS,versusgatevoltage,VGS,andtransconductance,Gm.

Impedancematchingwithidealelements–first-stage

Determinetheoptimalsourceandloadreflectioncoefficientstopresenttothefirst-stagedevice,basedonnoisefigureandgain.Ifnoiseisnotimportant,thenjustdesignforgain.ThesimulationsetupfromtheAmplifierDesignGuide(fromaschematic,DesignGuide>Amplifier>DCandBiasPointSimulations>FETNoiseFig.,S-Params,Gain,Stability,andCirclesvs.Bias)isshowninFigure5.

Inthissetup,thegateanddrainvoltagesareswept,andtheS-parametersandnoiseparametersofthefirststagedevicearesimulatedat10GHz,ateachbiaspoint.Thecorrespondingdatadisplayshowsnoise,gain,andstabilitycircles,whichareallupdated,dependingonthebiaspointyouselectwithamarker,asshowninFigure6.

Abouta1-dBnoisefigureand>16dBofgainshouldbeachievable,butthedeviceispotentiallyunstable,asindicated

bythesourcestabilitycirclebeingwell

withintheunitSmithchart. Figure5.TheFET_SP_NF_Match_Circschematic,forsimulatingadevice’sS-parameters,gain,noise

figure,andstabilityversusbias.

Figure6.Thegain,noise,andstabilitycirclesareplottedforthebiaspointselectedbymarkermBiasPt.

Attainingstabilitywithidealelements–first-stage

Feedbackelementsareaddedbetweenthegateandgroundandbetweenthegateanddrainofthefirst-stageFETtoimprovestability.OptimizethestabilitycircuitsusingtheGain_and_Stab_optschematicfromtheAmplifierDesignGuide(fromaschematic,DesignGuide>Amplifier>S-ParameterSimulations>FeedbackNetworkOptimizationtoAttainStability),asshowninFigure7.

Thissimulationincludesgoalstoforcethegeometricsourceandloadstabilityfactors,mu_sourceandmu_load,respectively,tobe>1overabroadfrequencyrange.[Ref.M.L.Edwardsand

J.H.Sinsky,"Anewcriterionforlinear2-portstabilityusinggeometricallyderivedparameters",IEEETransactionsonMicrowaveTheoryandTechniques,Vol.40,No.12,pp.2303-2311,Dec.1992.]

Ifthesestabilityfactorsare>1,thenneitherthesourcenorloadstabilitycircleintersectstheunitSmithchart.

Minimumnoisefigureandgainareincludedasoptimizationgoals,otherwiseperformancemightbedegradedtoomuchtoattainstability.Theresults,showninFigure8,showgoodstabilityperformanceandreasonablygoodgainandminimumnoisefigure,butwithideallumpedelements.

Figure7.OptimizationoffeedbackandshuntR,L,andCvaluestoattainstabilitywithoutdegradingnoisefigureandgaintoomuch.

Figure8.Gainandstabilityoptimizationresults.

Replaceidealelementswithdesignkitelements–first-stageReplacingtheidealelementsinthestabilizationnetworkwithdesignkitelementsshowsadegradationinstability.Werunadiscrete-valueoptimizationtoadjustthedesignkitelementstoattainbetterstability.Discrete-valueoptimizationisnecessaryifsomeoftheparameterstobeoptimizedmayhaveonlydiscretevalues,suchasthenumberofturnsofaspiralinductor.TheresultoftheoptimizationisshowninFigure9.

ToimprovestabilitynearDC,weaddeda10-Ohmresistorinserieswiththeinductorbiasingthegateofthedevice,atalaterstepinthedesign.Discrete-valueoptimizationcanbequitetime-consuming,sinceitcarriesoutanexhaustivesearchofallpossiblecombinationsofparametervalues.Itisrecommendedtofirstrunacontinuousoptimizationtogetidealelementvaluesasastartingpoint,andthenrunadiscrete-valueoptimization,allowingtheparametervaluestovaryoveronlyalimitedrange.Certaincontinuousoptimizationtypes(mainlyrandomanditsvariations)willhandlebothcontinuousanddiscreteoptimizablevariables.

Impedancematching–first-stagewithstabilizationnetworkDeterminetheoptimalsourceandloadimpedancestopresenttothestabilizedFET,viaS-parameterandnoisefiguresimulations,usingtheSP_NF_GainMatchKschematicfromtheAmplifierDesignGuide(fromtheschematicDesignGuide>Amplifier>S-ParameterSimulations>S-Params,Gain,NF,Stability,GroupDelayvs.

SweptParameters,showninFigure10).

Figure9.Discretevalueoptimizationresults,usingcomponentsfromtheDemoKit.

Figure10.Simulationtodeterminetheoptimalsourceandloadimpedancesforgainorminimumnoisefigureforthefirststagedevicewithstabilizationnetwork.

Thedatadisplay,showninFigure11,showsthatwithasourceimpedanceof21.3+j*3.7ohms,thenoisefigureisabout2.0dB.Withthissourceimpedance,thecorrespondingoptimalloadimpedanceis65.1+j*38.5ohms,whichshouldgiveatransducerpowergainof13.1dB.Itwaslaterdiscoveredexperimentallythatgeneratingaload

impedanceof39.5+j*52.9ohmsgivesahigherone-dBgaincompressionoutputpowerforthetwo-stageamplifier,attheexpenseoflowergain,sothisimpedancewasusedinstead.Ifgainismoreimportantthannoise,thenasourceimpedancetomaximizegaincouldbechosen.

Loadpull–secondstagedeviceForthesecondstagewewanttogeneratemoreoutputpower,soweexperimentwiththedevicesize.Adevicesizefourtimesaslargeas

thefirststagedevicewasselected,althoughalargerdeviceshouldgivemoreoutputpower.Aloadpullsimulation,HB1Tone_LoadPullMagPh,copiedfromtheexamples/RF_Board/LoadPull_prj,showed26.7dBmpowerdelivered,withaloadof7.76+j*9.7ohms,asshowninFigure12.(Additionalloadpullutilitiesareavailableintheloadpullapplication,underDesignGuide>Loadpull,fromaschematicwindow.)

Figure11.Gainandnoisecirclesandoptimalsourceandloadimpedancesforminimumnoisefigure.

Figure12.Loadpullsimulationresults.

Sourcepull–secondstage

Asourcepullsimulation,HB1Tone_SourcePull,fromtheAmplifierDesignGuide,indicatesthatthepowerdeliveredtotheloaddoesnotdependmuchonthesourceimpedance.Sotheinterstagematchingnetworkisdesignedtoprovidethecomplexconjugateasthesourceimpedancetopresenttothesecond-stageFET,whilethisFETisterminatedintheoptimalloadimpedancedeterminedfromtheload-pullsimulation.

Designingtheinputmatchingnetwork

Therearethreematchingnetworkstobedesigned:theinputtothefirststage,theinterstagebetweenthefirstandsecondstage,andtheoutputofthesecondstage.Thingstoconsiderinchoosingthesenetworksincludethesizeofthepassiveelements,incorporatingDCblockingcapacitors,andmakingsomeofthenetworkshigh-passandotherslow-pass,sotheoverallresponseisband-pass.

Becauseoftherelativelylowoperatingfrequency,distributed-elementmatchingwouldrequiretoomuchspace,soweuselumpedelementsinstead.Becausethisimpedancematchingisatasinglefrequencyonly,two-element,lumpedmatchingmayberealizedquitesimply.

ThePassiveCircuitDesignGuidewasusedtogenerateasimple,lumped-elementmatchingnetworktogeneratethedesiredsourceimpedance,asshowninFigure13,andtheresultingnetworkisasimpleshunt-C,series-Lnetwork.(NotethatthissamematchcanbefoundintheMatchingutilityortheSmithChartutility.)

Figure13.Theinputmatchingnetwork.

Figure14.Simulatingtheimpedanceofabiasnetwork.

Figure15.Biasnetworkimpedancesimulationresults.

Replaceidealelementswithdesignkitelements

Thenetworkwithidealelementsmustbereplacedwithdesignkitelements,whichhaveparasitics.Theparasiticsvarywiththesizeofeachcomponent.

YouwanttheDC-biasinductortobelargeenoughtoprovideahigh

impedanceat10GHz,butnotsolargethatitsparasiticcapacitancetogroundcausesaself-resonancetooccurbelowthisfrequency.Figure14showsthesetupforsimulationoftheimpedanceofasimplebiasnetwork.

TheresultsareshowninFigure15.

TheinputmatchingcircuitwithdesignkitelementsandaDCbiasnetworkisshowninFigure16.

ThecorrespondinglayoutisshowninFigure17.Sincethiscircuitisusedtobiasthegateofthefirst-stagedevice,thereshouldbelittleornobiascurrentdrawnfromthesupply,soaresistorcouldbeusedinsteadoftheinductor.ThishastheadditionalbenefitofsavingGaAsrealestate.

Figure16.Inputmatchingcircuitschematic,withdesignkitelementsandaDCbiasnetwork.

Figure17.Correspondinginputmatchingcircuitlayout,withdesignkitelementsandaDCbiasnetwork.

Interstagematch

Theinterstagenetworktransformstheinputimpedanceofthesecond-stagedevicetotheoptimalloadimpedancetopresenttothefirst-stagedevice.TheMatchingutilitywasusedtodesign

thesimpleshunt-C,series-Lmatchingnetwork(orthePassiveCircuitDesignGuidecouldbeused).TheInterstageMatch_wBiasnetworkisshowninFigure18.ItshowstheinterstagematchingnetworkincludingdesignkitelementsandDCbiasinductors.

Thelayout,showninFigure19,hasthedrainbiasinductorofthefirststageveryclosetothegatebiasinductorofthesecondstage,socouplingislikelytooccur.Theamountofcouplingand

towhatdegreeitdegradescircuitperformancecanbedeterminedfromaMomentum(electromagnetic)

simulation,althoughwedidnotperformoneforthisexample.

Figure18.Theinterstagematchingnetwork,includingdesignkitelementsandDCbiasinductors.

Figure19.Interstagematchingnetworklayout.

Outputmatch–secondstageTheoutputmatchingnetworkisusedtotransform50Ohmstotheoptimalloadimpedance(7.76+j*9.7Ohms)topresenttotheoutputofthesecondstagedevice.Anideal,shunt-L,series-Cnetworkiscreatedusingthe

OutputMatch1schematicintheexample,whichcamefromtheAmplifierDesignGuide(anotheroptionforgeneratingimpedancematchingnetworks).TheOutputMatch_wBiasschematic(intheexamplefile,andnotshownhere)usesdesignkitelementsinsteadofidealelements,andincludesaDCbiasinductor.

Interstagematchandstabilityverification–S-probe

Thenextstepistoverifythatwhenweconnectthematchingnetworks,inputdevicewithitsstabilizationnetwork,andoutputdevicethatwearegeneratingthedesiredsourceandloadimpedancesateachdevice.Also,weneedtoverifythatthestabilityconditionsaresatisfiedattheinputandoutputplanesofeachdevice.AnS-probeisusedtodeterminethesourceandloadimpedancesattheinputandoutputofeachdevice.

TheS-probeisanelementthatyoucaninsertanywhereintoacircuitwithoutloadingit.Itwilldeterminetheimped-ancesandreflectioncoefficientslookinginbothdirections.Fromthesereflectioncoefficients,wecandeterminewhetherthesmall-signalstabilityconditionsaresatisfiedornot.TheS-probepairschematicusedinthisexampleisshowninFigure20.

Inputmatchverification

TheTwoStgAmpInZ_TB,showninFigure21,determinesthesourceandloadreflectioncoefficientspresentedtothefirststagedevice.

Figure20.S-probepairschematic.

Figure21.Determiningtheimpedanceslookingbothdirections,attheinputandoutputofthefirststageFET.

ThedatadisplayinFigure22showsthattheseimpedancesareclosetothedesiredvaluesat10GHz,andthatthestabilityconditionsaresatisfiedfrom

10MHzto20GHz.

OutputmatchverificationTwoStgAmpOutZ_TB(showninFigure23)determinesthesourceandloadreflectioncoefficientspresentedtotheoutputdevice.

Figure22.Sourceandloadimpedancesclosetothedesiredvaluesarebeinggeneratedbythematchingnetworks.

Figure23.Two-stageamplifieroutputschematic.

ThedatadisplayinFigure24showsthattheloadimpedanceisclosetothedesiredvalueat10GHz,andthatthestabilityconditionsaresatisfiedfrom10MHzto20GHz.(Itisnecessarytocheckstabilityconditionsoverabroadfrequencyrange,beyondtheoperatingbandofinterest,tocheckforundesiredpotentialoscillations.)Also,thesource

impedancepresentedtotheinputofthedeviceisclosetothecomplexconjugateofthedevice’sinputimpedance

at10GHz.

Two-stageamplifiergaincompression

Next,aswept-powersimulationofthetwo-stageamplifierwithmatchingnetworkswascarriedouttodeterminethemaximumoutputpowerthatcouldbesupplied,power-addedefficiency,1-dBcompressionpoint,etc.ThissimulationisTwoStgAmp_TB,asshowninFigure25,andindicatesamaximumoutputpowerofabout

26.6dBmandanoutputpoweratthe1-dBgaincompressionpointofabout25dBm.ThissimulationsetupanddatadisplayarefromtheAmplifier

DesignGuide(DesignGuide>Amplifier>1-ToneNonlinearSimulations>Spectrum,Gain,HarmonicDistortionvs.Power(w/PAE)).TherearemanyothersimulationsetupsintheAmplifierDesignGuide,soyoucouldlookatthingslikeintermodulationdistortion,1-dB

gaincompression,frequencyresponse,andresponsesversussweptparametersaswell.

Figure24.Sourceandloadimpedancesclosetothedesiredvaluesarebeinggeneratedforthesecond-stagedevice,andthestabilityconditionsaresatisfied.

Figure25.Simulatingthegaincompressionandpower-addedefficiencyofthetwo-stageamplifier.

Branch-LineCouplerDesign

Branch-linecouplersareusedattheinputandoutput,tosplitthesignaltobesentthroughtwoparallel,identicaltwo-stageamplifiersandthentorecombinethesignalsattheoutput.Oneoftheadvantagesofthisapproachisthattheinputandoutputmatchesoftheoverallamplifieraregood,eventhoughthetwo-stageamplifiermay

bemismatchedattheinputoroutput.Also,youpotentiallycanobtain3dBhigheroutputpowerthanasingleamplifiercouldprovidebyitself.

Branch-linecouplersmaybeimplementedviaquarter-wavelengthtransmissionlinesasshowninFigure26.Butat10GHz,theselineswouldbe2-3millimeterslong.Soinstead,thetransmissionlinesarereplacedbyC-L-Cpinetworks,asshowninFigure26.Thevaluesfortheinductorsandcapacitorsaregivenbytheequationsinthefigure.

ExactvaluesfortheLsandCsarecomputedontheBLC_LumpedIdealschematic,showninFigure27.(Itisusefultohaveanidealbranch-linecoupler,becauseitcanbeusedtodeterminethebestperformancethattheamplifieriscapableofachieving,andtodeterminewhethertimeandeffortshouldbeexpendedonimprovingaphysicalbranch-linecouplerdesignoronthetwo-stageamplifier.)TheseLsandCswereconvertedtodesignkitcomponents,with

aresultingdegradationinperformance.

Figure26.TheBranch-linecoupler,implementedastransmissionlines,canbeimplementedusinga-networkequivalentcircuitforeachl/4section,usingtheequationsshown[Reference,"FoundationsforMicrostripCircuitDesign,"T.C.Edwards,JohnWileyandSons,1981,pg.10.]

Figure27.Abranch-linecouplerimplementedusingideal,lumpedelements.

Adiscrete-valueoptimizationwasrun(setupisBranchLineCoupDiscOpt)asshowninFigure28,toimprovetheper-formanceofthebranch-linecouplercircuitimplementedwithdesignkitcomponents.

ThesimulationresultsareshownintheBLC_Lumped_TBdatadisplay,asshowninFigure29.

Figure28.Setupforoptimizingthebranch-linecouplerperformance.Theoptimizablevariablesaredefinedinthesubcircuit,asshowninFigure30.

Figure29.Optimizedbranch-linecouplerperformance.

TheoptimizedparametervaluesareshownontheBLC_Lumpedschematic,showninFigure30.TheBLC_LumpedBk_to_Bk_TBisusedtodeterminetheinsertionlossaswellastheoverallfrequencyresponseoftwobranch-linecouplersconnectedbacktoback.Ideally,thislosswouldbe0dB,buttheactuallosswillreducetheideal

3-dBincreaseinoutputpowerthatthisbalancedamplifierconfigurationwouldachieveifthesewerelossless.Youcancompensateforlossduetotheinputbranch-linecouplerbyincreasingtheinputsignalpower,butyoucannotmakeupforthelossduetotheoutputcoupler.

Preliminarybalancedamplifierperformance(withoutincludinginterconnectparasitics)

Combiningthetwo-stageamplifiersandlumped-elementbranch-linecouplerstogether,wegetabalancedamplifier.ThisissimulatedinBalancedLumpedAmp_TB,andshowninFigure31.ThisisthesamesimulationsetupfromtheAmplifierDesignGuidethatwasusedtoevaluatethetwo-stageamplifier.Theresultsshowasaturatedoutputpowerofabout29dBm,andanoutputpoweratthe1-dBgaincompressionpointofabout26.5dBm.

Theseresultsarewithdesignkitcomponents,butwithoutincludinganytransmissionlineeffects.

Figure30.Optimizedbranch-linecouplerparametervalues.

Figure31.Simulatingthegain,power,andpower-addedefficiencyofthepreliminarybalancedamplifier.

Creatingthelayout

Thelayoutofeachsubcircuitwasdonebyinitiallyplacingdesignkitelementsintheschematic,thenusingtheLayout>PlaceComponentsFromSchemToLayoutcommandtomanuallyplacethecomponentsintothelayout.AfasteralternativeistheLayout>Generate/UpdateLayoutcommand,whichwillautomaticallyplacealloftheschematiccomponentsintothelayout.Aftercomponentswereplacedinthelayout,traceswereinserted(Insert>Tracecommand,orselectingthetoolbaricon)toconnectthemtogether.

LineCalcwasusedtodeterminethata70μmwidthwasneededfora50Ohmlineon100μmGaAs,andthata20-μmwidelineisabout77Ohms.ForRFinterconnects,thesetransmissionlinelengthsarekeptasshortaspossibletominimizeparasitics.

Inthelayout,viaswereinsertedwhereitwasnecessarytochangefromonemetallayertoanother.ThesewerethenplacedintheschematicviatheSchematic>PlaceComponentsFromLayoutToSchemcommand.

TheTools>CheckRepresentationcommand,showninFigure32,isquiteusefulforverify-ingthatallcomponentshavebeenplacedinboththelayoutandtheschematicandthattheirparametervaluesallmatch.

ErrorsarereportedasshowninFigure33.Whenplacingthesubcircuitsinthetop-levellayout,theEdit>EditInPlace>PushIntocommandisquiteusefulforaligningthepinsofdifferentsubcircuitsforfinalcon-nectionsaswellasforadjustingtheplacementofcomponentstoeliminateoverlapsandminimizewastedspace.

Figure32.Checkrepresentationdialogbox.

Figure33.Checkrepresentationerrordisplay.

AninitiallayoutofthecompleteamplifierisshowninBalancedLumpedAmplayout,

Figure34.Sincetheeffectsoftransmissionlineshavenotbeenincludedinthesimulationsyet,itisexpectedthatsomeadjustmentstothislayoutwillbenecessary.

Modelingtransmissionlineeffects–convertingtracestotransmissionlineelements

Toincludetheeffectsoftransmissionlines,thetracesinthelayout(whicharesimulatedasshortcircuits)mustbeconvertedtotransmissionlineelements.Todothis,acopyofeachsubcircuitwascreated,addingthesuffix“wTLs”tothedesignname(althoughthisisnotnecessary,itmakesiteasiertocomparethecircuitperformancewithandwithoutincludingtransmissionlineeffects.)AnMSUBcomponentforeachmetallayeronwhichtransmissionlineeffectsweretobeincludedwasplacedintotheschematic.EachMSUBcomponentwouldhaveadifferentmetallayernameforitsCond1parameter.Inthisdesign,allRFtracesareoneitherMetal1orMetal2,sotwoMSUBcompo-nentshavebeeninserted.(IftracesonMetal3aretobemodeledastransmissionlines,also,thenathirdMSUBcomponentisnecessary.)Somerealdesignkitsmighthavepre-definedMSUBcomponents;oneforeachmetallayer.

Ineachlayout,toconvertalltracesonaparticularlayer,doaSelect>SelectAllOnLayer...ThendoanEdit>Path/Trace/Wire>ConvertTraces...IntheTraceControldialogbox,showninFigure35,setConvertTracetoTransmissionlineelementsandentertheMSUBElementID(fromtheschematic)underSubstrateReferences.Whenthiscommandisexecuted,thetracesinthelayoutareconvertedtotransmission

lineelements.

Figure34.TheBalancedLumpedAmplayout.

Figure35.Tracecontroldialogbox.

Figure36showsasectionofalayoutaftertraceshavebeenconvertedtotransmissionlines.ThesetransmissionlinescanthenbeplacedintheschematicviatheSchematic

PlaceComponentsFromLayoutToSchemcommand.Thereareafewwaystodothis.First,youcanmanuallyplacethecomponentstocreateaschematicthatlookssimilartoyourlayout,anditenablesyoutofindkeytransmissionlinesandtesttheeffectsofvaryingthemonperformance.Anotheroptionistouselayoutlook-alikecomponentstocreateschematicsymbolsthatlookthesameasthepassivepartsofyourlayout.Withthismethod,aMomentumsimulationisautomaticallylaunchedtogenerateamodelforeachlook-alikecomponent,buttheMomentumsimulationonlyhastoberunonce,aslongasyoudon’tmodifythelayout.Thisshouldgivethemostaccuratesimulationresults.

Alternatively,youcanskipplacingthetransmissionlinecomponentsontotheschematicandinsteadselectSimulatefromLayoutintheDesignParametersdialog(File>DesignParameters),asshowninFigure37.

Figure36.Partofalayoutafterconvertingtracestotransmissionlines.

Figure37.DesignParametersdialogbox,allowingyoutospecifythatthelayoutrepresentationbeusedforthesimulation.

Compensatingfortransmissionline