1、 多功能數字鐘設計說明：1系統頂層框圖： 各模塊電路功能如下：1.秒計數器、分計數器、時計數器組成最基本的數字鐘，其計數輸出送7段譯碼電路由數碼管顯示。2.基準頻率分頻器可分頻出標準的1HZ頻率信號，用于秒計數的時鐘信號；分頻出4HZ頻率信號，用于校時、校分的快速遞增信號；分頻出64HZ頻率信號，用于對按動“校時”，“校分”按鍵的消除抖動。2.多功能數字鐘結構框圖：一、系統功能概述已完成功能1. 完成時分秒的依次顯示并正確計數，利用六位數碼管顯示；2. 時分秒各段個位滿10正確進位，秒分能做到滿60向前進位，有系統時間清零功能；3. 定時器：實現整點報時，通過揚聲器發出高低報時聲音；4. 時間

2、設置，也就是手動調時功能：當認為時鐘不準確時，可以分別對分時鐘進行調整；5. 鬧鐘：實現分/時鬧鐘設置，在時鐘到達設定時間時通過揚聲器響鈴。有靜音模式。 待改進功能：1. 系統沒有萬年歷功能，正在思考設計方法。2. 應添加秒表功能。二、系統組成以及系統各部分的設計1.時計數模塊時計數模塊就是一個2位10進制計數器，記數到23清零。VHDL的RTL描述如下：-cnt_h.vhdlibrary ieee;entity cnt_h is port(en,clk,clr:in std_logic; dout:out std_logic_vector(7 downto 0); c:out std_log

3、ic);end cnt_h;architecture rtl of cnt_h issignal t:std_logic_vector(7 downto 0);begin process(en,clk,clr) variable t:std_logic_vector(7 downto 0); begin if en='1' then -異步使能 if clk 'event and clk='1' then t:=t+1; if t(3 downto 0)=X"A" then -個位等于10則十位加1 t(7 downto 4):=t(

4、7 downto 4)+1; t(3 downto 0):=X"0" -個位清零 end if; if t>X"23" then -大于23清零 t:=X"00" end if; end if; if clr='1' then -異步清零 t:=X"00" end if; end if; dout<=t; end process;end rtl;時計數器模塊仿真波形如下從仿真波形可知，當計數到23時，下一個時鐘上升沿到來時就清零了，符合設計要求。時計數模塊框圖如下2. 分及秒計數模塊分及

5、秒計數模塊也是一個2位10進制計數器，記數到59清零。VHDL的RTL描述如下：library ieee;entity cnt_s is port(en,clk,clr:in std_logic; dout:buffer std_logic_vector(7 downto 0); c:out std_logic);end cnt_s;architecture rtl of cnt_s isbegin process(en,clk,clr) begin if en='1' then if clr='1' then -異步清零 dout<=X"00&

6、quot; elsif clk 'event and clk='1' then if dout(3 downto 0)<9 then dout(3 downto 0)<=dout(3 downto 0)+1; c<='0' elsif dout(7 downto 4)<5 then dout(3 downto 0)<=X"0" dout(7 downto 4)<=dout(7 downto 4)+1; else dout<=X"00" c<='1' e

7、nd if; end if; else dout<="ZZZZZZZZ" end if; end process;end rtl;分和秒計數器模塊仿真波形如下從仿真波形可知，當計數到59時，下一個時鐘上升沿到來時就清零了，并且產生進位信號，符合設計要求。分和秒計數模塊框圖如下3. 按鍵消抖動模塊按鍵消抖動有很多方案，這里選擇的是計數消抖，即只當有效電平到來后開始計數，當計數值大于一定值后再輸出該有效電平，否則不輸出，從而達到消抖目的。VHDL的RTL描述如下：library ieee;entity haoin is port(din,clk:in std_logic;

8、 dout:out std_logic);end haoin;architecture rtl of haoin isbegin process(din) variable t: integer range 0 to 63:=0; begin if din='1' then if clk 'event and clk='1'then t:=t+1; if t>10 then dout<='1't:=t-1; else dout<='0' end if; end if; else dout<='

9、;0't:=0; end if; end process;end rtl;library ieee;entity ring is port( clk: in std_logic; clk500: in std_logic; clk1k:in std_logic; beep:out std_logic);end ring;architecture rtl of ring isbegin process(clk) variable t: std_logic; variable n: integer range 0 to 15:=0; begin if clk 'event and

10、clk='1' then t:=not t;n:=n+1; end if; if t='1' and n<11 then beep<=clk500; elsif n=11 then beep<=clk1k; else beep<='Z' end if; end process;end rtl;library IEEE; entity clock is port( SA: in std_logic; SB: in std_logic; SC: in std_logic; SD: in std_logic; clk1: in

11、std_logic; dout: buffer std_logic_vector(23 downto 0); -seg_data:out std_logic_vector(7 downto 0); -seg_com:out std_logic_vector(3 downto 0); beep: out std_logic -led:out std_logic_vector(3 downto 0) );end entity clock;architecture rtl of clock is component cnt_s is port(en,clk,clr:in std_logic; dou

12、t:buffer std_logic_vector(7 downto 0); c:out std_logic); end component; component cnt_h is port(en,clk,clr:in std_logic; dout:buffer std_logic_vector(7 downto 0) ); end component; -component segmain is -port(clk,reset_n:in std_logic; -datain:in std_logic_vector(15 downto 0); -seg_data:out std_logic_

13、vector(7 downto 0); -seg_com:out std_logic_vector(3 downto 0); -end component; -component ring is -port( en: in std_logic; - clk: in std_logic; -clk500: in std_logic; -clk1k:in std_logic; -beep:out std_logic); -end component; component haoin is port(din,clk:in std_logic; dout:out std_logic); end com

14、ponent; component naoling is port (h,m:in std_logic_vector(7 downto 0); clk4hzh,clk4hzm:in std_logic; sys_en,sys_rst:in std_logic; h_o,m_o: out std_logic_vector(7 downto 0); beep:out std_logic); end component; signal reg_h:std_logic_vector(7 downto 0); signal reg_m:std_logic_vector(7 downto 0); sign

15、al reg_s:std_logic_vector(7 downto 0); signal reg_m_s:std_logic_vector(7 downto 0):=X"59" signal reg_m_m:std_logic_vector(7 downto 0):=X"59" signal reg_m_h:std_logic_vector(7 downto 0):=X"59" signal clk_h:std_logic; signal clk_m:std_logic; signal clk_s:std_logic; signal

16、 c_s :std_logic; signal c_m :std_logic; signal c_h :std_logic; signal sys_clk1:std_logic; signal sys_clk4:std_logic; signal sys_clk64:std_logic; signal sys_clk500:std_logic; signal sys_clk1k:std_logic; signal clki:integer:=750000; signal sys_rst:std_logic:='0' signal sys_en:std_logic:='1

17、' signal clk_ring,mh:std_logic; signal SAc,SBc,SCc,SDc:std_logic; signal en_r:std_logic; signal NL_reg_h,NL_reg_m:std_logic_vector(7 downto 0); signal NL_ring:std_logic; signal sys_clk4_NL_h,sys_clk4_NL_m:std_logic;begin h:cnt_h port map(en=>sys_en,clk=>clk_h,clr=>sys_rst,dout=>reg_h

18、); m:cnt_s port map(en=>sys_en,clk=>clk_m,clr=>sys_rst,dout=>reg_m,c=>c_m); s:cnt_s port map(en=>sys_en,clk=>sys_clk1,clr=>SCc,dout=>reg_s,c=>c_s); -sled:segmain port map(clk=>clk1,reset_n=>SCc,seg_data=>seg_data,seg_com=>seg_com,datain=>dout(15 downto 0)

19、; -ring0:ring port map(en=>en_r,clk=>clk_ring,clk500=>sys_clk500,clk1k=>sys_clk1k,beep=>beep); haoin1:haoin port map( SA,sys_clk64,SAc); haoin2:haoin port map( SB,sys_clk64,SBc); haoin3:haoin port map( SC,sys_clk64,SCc); haoin4:haoin port map( SD,sys_clk64,SDc); NL:naoling port map(be

20、ep=>NL_ring,h=>reg_h,m=>reg_m,clk4hzh=>sys_clk4_NL_h,clk4hzm=>sys_clk4_NL_m,sys_en=>sys_en,sys_rst=>sys_rst,h_o=>NL_reg_h,m_o=>NL_reg_m); beep<=clk_ring and mh; -led<=reg_s(3 downto 0); p_sys_clk:process(clk1) variable t1,t4,t64,t500,t1k:integer range 0 to 50000000;

21、begin if clk1 'event and clk1='1' then t1:=t1+1; t4:=t4+1; t64:=t64+1; t500:=t500+1; t1k:=t1k+1; if t1=clki/2 then t1:=0; sys_clk1<=not sys_clk1; end if; if t4=clki/8 then t4:=0; sys_clk4<=not sys_clk4; end if; if t64=clki/128 then t64:=0; sys_clk64<=not sys_clk64; end if; if t5

22、00=clki/1000 then t500:=0; sys_clk500<=not sys_clk500; end if; if t1k=clki/2000 then t1k:=0; sys_clk1k<=not sys_clk1k; end if; end if; end process p_sys_clk; p_c:process(SAc,SBc,SCc,SDc) begin if SAc='1' and SDc='0' then clk_h<=sys_clk4; else clk_h<=c_m; end if; if SAc=&#

23、39;1' and SDc='1' then sys_clk4_NL_h<=sys_clk4; else sys_clk4_NL_h<='0' end if; if SBc='1' and SDc='0'then clk_m<=sys_clk4; else clk_m<=c_s; end if; if SBc='1' and SDc='1'then sys_clk4_NL_m<=sys_clk4; else sys_clk4_NL_m<='0' end if; if SDc='0' then dout(7 downto 0)<=reg_s; dout(15 downto 8)<=reg_m; dout(23 downto 16)<=r