UnitTwo■主要內(nèi)容：集成電路設(shè)計(jì)基礎(chǔ)知識，半導(dǎo)體制造技術(shù)，集成電路封裝測試技術(shù)，SMT表面貼裝技術(shù)等。■學(xué)習(xí)目標(biāo)：掌握集成電路設(shè)計(jì)的基本流程，著重掌握版圖設(shè)計(jì)、版圖驗(yàn)證的基本知識，掌握反相器版圖的繪制過程。了解現(xiàn)代集成電路設(shè)計(jì)基本方法，半導(dǎo)體制造工藝的基本流程，集成電路封裝測試的種類及過程等，掌握基本術(shù)語。■素質(zhì)目標(biāo)：“微世界，大情懷”，激發(fā)科技報(bào)國信念，提升思想境界；培養(yǎng)學(xué)習(xí)新技術(shù)和新知識的自主學(xué)習(xí)能力。Lesson4TheDesignofICLayout■IntegratedCircuit(IC)集成電路■IP知識產(chǎn)權(quán)■SystemonChip（SoC）片上系統(tǒng)■ASIC專用集成電路■VLSI超大規(guī)模集成電路■DSP數(shù)字信號處理

■FPGA現(xiàn)場可編程門陣列■CPLD復(fù)雜可編程器件■FrontEnd(FE)前端■BackEnd(BE)后端■Design設(shè)計(jì)■EDA電子設(shè)計(jì)自動(dòng)化■RTL寄存器傳輸級■Netlist網(wǎng)表■Foundry[’fa?ndri:]代工廠■CAD計(jì)算機(jī)輔助設(shè)計(jì)

■Layout[’leiaut]版圖■CIW命令解釋窗口■LSW層選擇窗口

Keywords■DRC設(shè)計(jì)規(guī)則檢查■LVS版圖與電路圖的對照■Match匹配■Active有源區(qū)■Source源■Drain[drein]漏

■Gate柵■Well[wel]阱

■Metal[metl]金屬■Resistance[ri’zist?ns]電阻■Capacitance[k?’p?s?t?ns]電容

■Inductance[in’d?kt?ns]電感■Contact[’k?nt?kt]連接■Design[di’zain]設(shè)計(jì)■Diode[’dai?ud]二極管■Bipolar[’p?r?’s?t?k]三級管■Parasitic寄生■Parameters[p?’r?mit?]參數(shù)■Schematic[ski:’m?t?k]電路■工作任務(wù)：什么是集成電路？集成電路事怎樣設(shè)計(jì)的？■學(xué)習(xí)目標(biāo)：掌握集成電路的設(shè)計(jì)流程■重點(diǎn)難點(diǎn)：版圖設(shè)計(jì)與版圖驗(yàn)證■推薦學(xué)時(shí)：8學(xué)時(shí)工作任務(wù)：WhatistheIntegratedCircuit?AndhowtheIntegratedCircuitbedesigned?Aseveryoneknows,theintegratedcircuitisasinglecomponentincludingalargenumberofactiveandpassivedevicesandtheirinterconnectionstorealizecomplexfunctions.Today,theintegratedcircuitsareusedinvariousaspectsoflife,suchascellphone、computer、DV、TV、buscardandsoon.Ourlifecan’tbeseparatedfromtheintegratedcircuit.

課文

1：ICdesignflowFig4–3DesignAbstractionLevelsFig4–4ICdesignflowTheICdesignflowasshowninFig5-4.Let’sbuildadigitalchip,wewillfollowadesignteamastheyprogressfromconcept,throughcircuittesting,andfinallytotheactualgateplacementandwiringofadigitalchip,usingasuiteofsoftwaretools.Firstyoudesignyourlogic,synthesizeit,draftafloor-plan,andthendosometimingchecksaroundthatloopforwhile.CircuitdesignerstypicallyuselanguagescalledVHDLtodesigntheirenormousdigitalcircuits.TheyuseVHDLlanguagetocreateachipthatexistsfirstasonlyadatabaseofnumbers.TheseVHDLdatafilesarethensubmittedtoacomputersimulator,whichteststhechipcircuitrywhileitisstillinsoftwareform.BylookingattheresultsoftheseVHDLsimulations,wecanmakeadjustmentstothecircuitrybeforewecommitthechiptoactualsilicon.Thisisagreatsaving.Oncethecircuitdesignerhasfinishedverifyinghislogicdesign,hewillputhisVHDLcodethroughasiliconcompilerorlogicsynthesizer.ThecompilertranslatesthehighlevelC-likecodeintoafilethatcontainsalltherequiredlogicfunctions,aswellashowtheyaretobeconnectedtoeachother.Atthispoint,weknowthatgatesweneed,andweknowhowtheyeventuallywiredtoeachother.Thisfile,calledanetlist,willdriveyouautomatedlayouttools.Wearenowreadytostartthelayoutprocess,webeginfloorplanning.Thenyourunyourplaceandroutetoolsanddosometimingchecks.Youkeepgoingaroundthatloopuntilyouarehappy.Youmayevenhavetogoaroundthefloor-planloopacoupleoftimesagain.Atthispoint,youneedthedigitallibraries.BylibraryImeantheAND’s,OR’s,inputcells,outputcells,andalltherealtransistorlevelcomponents.YouneedthedigitallibrariestomakeyourfinalGDSIIfile.Finally,youruntheDRCandLVSchecksagainstthenetlistyoustartedwith,outofyourlogicsynthesis.ThenyougetthefinalchipdoneFig4–5LayoutDesignLayoutdesigntechniqueshavedevelopedatanenormousrate.Asintegratedcircuitspeedsincrease,thelayoutdesignerisexpectedtoquickly、efficiently,andaccuratelytranslateaschematicintolayout,makeinformedchoicesbasedonknowledgeofincreasinglycomplextools,andunderstandhowcircuitfunctioncanaffectlayoutdecisions.Layoutdesignhasevolvedintoahighlyvaluedprofession.ThelayoutdesignisgettingtheICdesignontosilicon,asshowninfig5-5,theplaceandroutetoolscanhelpus.Placeandroutetoolscoverthegamutofhigherlevelandlowerlevelsoftwareassistanceleadingtoyourfinallayout.Areyourskillsassharpastheycouldbe?Areyouhighlyvalued?First,youneedtocompletelyunderstandyoucircuit,bothelectricallyandphysically.Second,youneedtounderstandyourmanufacturingprocessintimately-howeverycomponentintheprocessisbuiltandused.Aboveall,makesurethatlayoutdesignersgetalltheinformationneedtodotheirjobeffectively.Severalkindsoflayout：3：Layoutverification----DRC、LVSTherearelotsofdesignrulesinlayout,youonlyneedoneteeny、tiny、littlemistaketocompletelykillyourchip.Withcycletimesinatypicalwaferfabtaking8to12weeks,andawafercostingthousandsofdollars,youwantmakesurethatwhatyoucommittosiliconiscorrect.Howtomakesureyouhaveclearedeachandeveryone?weneedlayoutverification.Tohelpuswatchallourrules,mosttoolsnowadayshavecompute-aidedruleandlayoutcheckers.Yousomehowenterallofthethousandsofrulesintothesoftware.Thecomputergoesawayandchecksyourlayoutagainsttheserulesforyou.DRC(DesignRuleCheck)：TheDRCprogramknowseverythingthereistoknowaboutyourprocess.Itwillgoawayanddiligentlycheckeverythingthatyouhavelaidout.ADRCprogramTypicallywillputbackintoyourlayoutabunchoferrormarkers.These

arehighlightsonthelayoutlocatingyourerrors.LVS（LayoutVersusSchematic）:ExtensionstodesignrulecheckingsoftwarethatarefoundinLVSactuallycreaterealcomponentsandcircuits.MostpeoplecalltheprocessLVS,butinreality,itisnotjustlayoutversusschematic.Itisatow-stepprocess.ThefirstpartoftheLVSprocessistheextractionofthedeviceinformationfromthelayout.ThesecondpartoftheLVSprocessisthecomparison.Thetoolextractsanetlistofthedevicesthatitfindsfromthelayout,thengeneratesnetlistfromtheschematic,thencomparesthosetwonetlists.4：LayoutTutorial-------CreatingaInverterlayout

InthistutorialyouwillgothroughcreatingaInverterlayout,performingdesignrulechecks(DRC).Extractingconnectivityandverifyingthelayout