1、 預(yù)做實(shí)驗(yàn)報(bào)告1運(yùn)算器設(shè)計(jì)與仿真一、實(shí)驗(yàn)?zāi)康睦斫獠⒄莆者\(yùn)算器的基本電路結(jié)構(gòu)及其設(shè)計(jì)方法，學(xué)會(huì)使用VerilogHDL對(duì)電路進(jìn)行行為建模、結(jié)構(gòu)建模以及仿真測(cè)試。二、實(shí)驗(yàn)內(nèi)容利用VerilogHDL設(shè)計(jì)一個(gè)運(yùn)算器模型，并進(jìn)行仿真測(cè)試。要求該運(yùn)算器的字長(zhǎng)為32位，能夠?qū)崿F(xiàn)加法、減法、邏輯與、邏輯或四種運(yùn)算，并產(chǎn)生N（結(jié)果為負(fù)）、Z（結(jié)果為零）、V（結(jié)果溢出）、C（進(jìn)位）四個(gè)標(biāo)志位。要求采用層次化的建模方法，即先搭建低層模塊，然后再逐級(jí)搭建高層模塊。三、實(shí)驗(yàn)環(huán)境PC機(jī)1臺(tái)、Modelsim仿真軟件1套。四、實(shí)驗(yàn)步驟1、電路結(jié)構(gòu)設(shè)計(jì)ALU的電路結(jié)構(gòu)OP00AND01OR1位全加器邏輯表達(dá)式：S=abCj

2、+abCj+abCj+abCfabciCo=abc+abc+abc+abc=ab+ac+bciiiiiiaHL-s7-Docs其中：Sub=0,做加法，Sub=1,做減法。2、建立Verilog模型modulefadd(a,b,s,ci,co);inputa,b,ci;outputs,co;regs,co;always(aorborci)begins=(a&b&ci)|(a&b&ci)|(a&b&ci)|(a&b&ci);co=(a&b)|(a&ci)|(b&ci);endendmodulemoduleadd(a,b,sub,s,c,v,n);input31:0a;input31:0b;inp

3、utsub;output31:0s;outputc,v,n;wire31:0a;wire31:0b;wirec1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31;faddf0(a0,b0Asub,s0,sub,cl);faddf1(a1,b1Asub,s1,c1,c2);faddf2(a2,b2Asub,s2,c2,c3);faddf3(a3,b3Asub,s3,c3,c4);faddf4(a4,b4Asub,s4,c4

4、,c5);faddf5(a5,b5Asub,s5,c5,c6);faddf6(a6,b6Asub,s6,c6,c7);faddf7(a7,b7Asub,s7,c7,c8);faddf8(a8,b8Asub,s8,c8,c9);faddf9(a9,b9Asub,s9,c9,c10);faddf10(a10,b10Asub,s10,c10,c11);faddf11(a11,b11Asub,s11,c11,c12);faddf12(a12,b12Asub,s12,c12,c13);faddf13(a13,b13Asub,s13,c13,c14);faddf14(a14,b14Asub,s14,c14

5、,c15);faddf15(a15,b15Asub,s15,c15,c16);faddf16(a16,b16Asub,s16,c16,c17);faddf17(a17,b17Asub,s17,c17,c18);faddf18(a18,b18Asub,s18,c18,c19);faddf19(a19,b19Asub,s19,c19,c20);faddf20(a20,b20Asub,s20,c20,c21);faddf21(a21,b21Asub,s21,c21,c22);faddf22(a22,b22Asub,s22,c22,c23);faddf23(a23,b23Asub,s23,c23,c2

6、4);faddf24(a24,b24Asub,s24,c24,c25);faddf25(a25,b25Asub,s25,c25,c26);faddf26(a26,b26Asub,s26,c26,c27);faddf27(a27,b27Asub,s27,c27,c28);faddf28(a28,b28Asub,s28,c28,c29);faddf29(a29,b29Asub,s29,c29,c30);faddf30(a30,b30Asub,s30,c30,c31);faddf31(a31,b31Asub,s31,c31,c);assignn=s31;assignv=cAc31;endmodule

7、modulemux21_32(f,a,b,s);output31:0f;input31:0a,b;inputs;reg31:0f;always(soraorb)case(s)1d0:f=a;1d1:f=b;endcaseendmodulemoduleALU(op,a,b,s,n,v,c,z);input1:0op;input31:0a,b;output31:0s;outputn,v,c,z;wire31:0d,e,f,s1;assignd=a&b;assigne=a|b;mux21_32u0(f,d,e,op0);addu2(a,b,op0,s1,c,v,n);mux21_32u1(s,f,s

8、1,op1);assignz=(|s);endmodule3、設(shè)計(jì)測(cè)試文件timescaleIns/InsmoduleALUtest;regclk;reg1:0op;reg31:0a,b;wire31:0s;wiren,v,c,z;/op=00AND;/op=01OR;/op=10ADD;/op=11SUB;ALUA(op,a,b,s,n,v,c,z);/clockgenerationinitialclk=1;always#50clk=clk;initialbegin#20a=32b0100_0101_0100_0000_0010_0010_0101_0001;b=32b1010_0101_0

9、010_0000_0100_0010_0011_0010;op=2b00;#100a=32b0100_0101_0100_0000_0010_0010_0101_0001;b=32b1010_0101_0010_0000_0100_0010_0011_0010;op=2b01;#100a=32b0100_0101_0100_0000_0010_0010_0101_0001;b=32b1010_0101_0010_0000_0100_0010_0011_0010;op=2b10;#100a=32b0100_0101_0100_0000_0010_0010_0101_0001;b=32b1010_

10、0101_0010_0000_0100_0010_0011_0010;op=2b11;#100a=32b0111_1011_1101_1110_1111_1111_1111_1111;b=32b0111_1011_1101_1110_1111_1111_1111_1111;op=2b11;#100a=32d15;b=32d9;op=2b11;#100a=32d9;b=32d15;op=2b11;#100$stop;endEndmodule$display(a=%b,b=%b,op=%b,s=%b,n=%b,z=%b,v=%b,c=%bn,a,b,op,s,n,z,v,c);注意：測(cè)試的完備性。4、將設(shè)計(jì)文件和測(cè)試文件輸入Modesim仿真工具，并進(jìn)行編譯和功能仿真。5、觀測(cè)仿真波形圖，分析結(jié)果是否正確。若有錯(cuò)誤，則修改