1、library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity counter is Port ( clk : in std_logic; resetn : i

2、n std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic);end counter;architecture Behavioral of counter iscomponent counter60 isPort ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0);end component

3、;component decoder is Port (din:in std_logic_vector(3 downto 0 ); dout:out std_logic_vector(8 downto 0) ); end component;component lcd_interface is port ( clk : in std_logic; resetn : in std_logic;dout_s10 : in std_logic_vector (8 downto 0);dout_s1 : in std_logic_vector (8 downto 0); lcd_data : out

4、std_logic_vector (7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic );end component; signal ddout_s10 : std_logic_vector (8 downto 0); signal ddout_s1 : std_logic_vector (8 downto 0); signal ddout : std_logic_vector (7downto 0);beginu1: counter60 port map(clk,resetn

5、,ddout);u2: decoder port map(ddout(7 downto 4),ddout_s10); u3: decoder port map(ddout(3 downto 0),ddout_s1);u4: lcd_interface port map(clk,resetn, ddout_s10,ddout_s1,dout,lcd_en, lcd_rs , lcd_rw);end Behavioral;- Company: - Engineer:- Create Date: 13:36:10 03/30/06- Design Name: - Module Name: count

6、60 - Behavioral- Project Name: - Target Device: - Tool versions: - Description:- Dependencies:- - Revision:- Revision 0.01 - File Created- Additional Comments:- -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter60 is Port ( clk : in

7、std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0);end counter60;architecture Behavioral of counter60 issignal count : std_logic_vector(7 downto 0);signal count_div : std_logic_vector (25 downto 0);begin dout = count; process (clk) begin if (clkevent and clk = 1) then if (rese

8、tn = 0) then count_div 0); else if (count_div (25) = 1) then count_div 0);else count_div = count_div + 1; end if; end if; end if; end process;process(clk ,resetn)begin if resetn= 0 then count 0); elsif rising_edge(clk) then if (count_div (25) = 1) then if count(3 downto 0)=1001 then count(3 downto 0

9、)=0000;count(7 downto 4)=count(7 downto 4) +1; elsecount(3 downto 0)=count(3 downto 0)+1; end if; if count=01011001 then count dout dout dout dout dout dout dout dout dout dout dout=100100000;end case;end process;end Behavioral;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;us

10、e ieee.std_logic_unsigned.all;entity lcd_interface is port ( clk : in std_logic; resetn : in std_logic;dout_s10 : in std_logic_vector (8 downto 0);dout_s1 : in std_logic_vector (8 downto 0); lcd_data : out std_logic_vector (7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out st

11、d_logic );end lcd_interface;architecture lcd_interface_arch of lcd_interface issignal lcd_we_n : std_logic;signal lcd_en_int : std_logic;signal w_comp_n : std_logic;signal seq_count : std_logic_vector (5 downto 0);signal lcd_rs_data : std_logic_vector (8 downto 0);signal delay_count : std_logic_vect

12、or (15 downto 0);signal lcd_addr : std_logic_vector (5 downto 0);type state_lcd_write_type is (lcd_write_idle, lcd_write_1, lcd_write_2, lcd_write_3, lcd_write_4);signal state_lcd_write : state_lcd_write_type;type state_type is (idle, wait_1, wait_2, state_1, state_2, state_3, done);signal state : s

13、tate_type; begin- The following state machine initializes the LCD and writes the following message - to the LCD panel- Memec Design- MB1000 Board- The LCD initialization sequence consist of writing the 0x38, 0x38, 0x06, 0x0e,- 0x01, 0x80, 0xc0 sequence of hex numbers to the LCD control registers (pl

14、ease- refer to the LCD datasheet for an explanation of the initialization sequence).- At the end of the LCD initialization sequence, the LCD is ready to be written- to starting with line 1. It should be noted that delays are inserted between- 2 writes to the LCD panel to meet the LCD initialization

15、requirements. Although,- the LCD panel requires different delays between 2 writes, a fix delay of 20ms is- inserted between 2 writes to simply the initialization design (the 20ms is the- longest delay that is required by the LCD panel). A 22-bit counter is used to- generate this fix delay. sequencer

16、_state_register: process (clk, resetn) begin if (resetn = 0) then state if (delay_count(15) = 1) then state = wait_1; else state if (delay_count(15) = 1) then state = state_1; else state state if (w_comp_n = 0) and (lcd_addr = 000110) then state = wait_2; elsif (w_comp_n = 0) then state = wait_1; el

17、se state if (delay_count(15) = 1) then state = state_3; else state if (w_comp_n = 0) and (lcd_addr = 100111) then state = done; elsif (w_comp_n = 0) then state = wait_2; else state state lcd_we_n lcd_we_n lcd_we_n lcd_we_n lcd_we_n lcd_we_n lcd_we_n = 1; end case; end process sequencer_state_logic;-

18、 The following sections uses the lcd_we_n signal to generate the lcd_en signal and- a write complete signal (w_comp_n). The w_comp_n signal is used to reset various- counters that are used to generate LCD control signals. state_lcd_write_register: process (clk, resetn) begin if (resetn = 0) then sta

19、te_lcd_write if (lcd_we_n = 0) then state_lcd_write = lcd_write_1; else state_lcd_write if (seq_count = 000101) then state_lcd_write = lcd_write_2; else state_lcd_write if (seq_count = 011110) then state_lcd_write = lcd_write_3; else state_lcd_write if (seq_count = 110010) then state_lcd_write = lcd

20、_write_4; else state_lcd_write state_lcd_write lcd_en_int = 0; w_comp_n lcd_en_int = 0; w_comp_n lcd_en_int = 1; w_comp_n lcd_en_int = 0; w_comp_n lcd_en_int = 0; w_comp_n lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_d

21、ata lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data lcd_rs_data = 100100000; end case;end process;- The following is a 22-bit free running counter that is cleared when the reset- signal is asserted or the MSB of the counter goes to 1. This

22、counter is used- to generate delays between back-to-back writes to the LCD panel during the - initialization and also normal write cycles. process (clk) begin if (clkevent and clk = 1) then if (resetn = 0) then delay_count 0); else if (delay_count(15) = 1) then delay_count 0);else delay_count = dela

23、y_count + 1; end if; end if; end if; end process;- The following counter is used by the sequencer to generate the lcd_en signal.- The counter is reset at the end of each write to the LCD when the w_comp_n- signal goes active. process (clk) begin if (clkevent and clk = 1) then if (resetn = 0) or (w_comp_n = 0) then seq_count 0); elsif (lcd_we_n = 0)