1、.現(xiàn)代電子與系統(tǒng)設(shè)計總結(jié)報告現(xiàn)代電子與系統(tǒng)設(shè)計總結(jié)報告項目名稱： 乒乓球比賽游戲機(jī)班 級： 物科院1005姓 名： 周* 沈*學(xué) 號： 071005* 071005*指導(dǎo)老師： 倪*提交日期： 2012/12/23封面1一、設(shè)計要求3二、設(shè)計的具體實現(xiàn).31、系統(tǒng)框圖.32、甲乙方得分顯示模塊.43、加減計數(shù)模塊.64、譯碼模塊.85、控制模塊.96、核心問題.12三、結(jié)果分析.15四、附件161、完整電路圖.162、各個自制元件的VHDL程序.16一、設(shè)計要求設(shè)計一個乒乓球比賽游戲機(jī)（1）設(shè)計一個由甲乙雙方參加，有裁判的三人乒乓球游戲機(jī)；（2）用8個（或更多個）LED排成一條直線，以中點(diǎn)為界

2、，兩邊各代表參賽雙方的位置，期中一只點(diǎn)亮的LED指示球的當(dāng)前位置，點(diǎn)亮的LED依次從左到右，或從右到左，其移動的速度應(yīng)能調(diào)節(jié)；（3）當(dāng)“球”（點(diǎn)亮的那支LED）運(yùn)動到某方的最后一位時，參賽者應(yīng)能果斷地按下位于自己一方的按鈕開關(guān)，即表示啟動球拍擊球，若擊中則球向相反方向移動，若未擊中，球掉出桌外，則對方得一分；（4）設(shè)計自動計分電路，甲乙雙方各用兩位數(shù)碼管進(jìn)行計分顯示，每記滿11分為1局；（5）甲乙雙方各設(shè)一個發(fā)光二極管表示擁有發(fā)球權(quán)，每隔2次自動交換發(fā)球權(quán)，擁有發(fā)球權(quán)的一方發(fā)球才有效；（6）其他。二、設(shè)計的具體實現(xiàn)1、系統(tǒng)框圖此系統(tǒng)框圖分為控制模塊，加/減計數(shù)模塊，譯碼顯示模塊和甲乙方得分顯示

3、模塊。2、甲乙方得分顯示模塊甲乙雙方各用兩位數(shù)碼管進(jìn)行計分顯示，通過控制模塊加以控制。甲乙得分的計數(shù)：圖形：VHDL語言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jifen ISPORT(reset : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jifen;ARCHITECTURE jifen_architecture OF jifen ISBEGIN process

4、(clk,reset) begin if(reset='0') then q<="0000" elsif(clk'event and clk='1') then if(q="1011") then q<="1011" else q<=q+1; end if; end if; end process;END jifen_architecture;甲乙得分的顯示：圖形：VHDL語言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.

5、std_logic_unsigned.all;ENTITY xianshi ISPORT(a : IN STD_LOGIC_VECTOR(3 downto 0);y1 : OUT STD_LOGIC_VECTOR(6 downto 0);y0 : OUT STD_LOGIC_VECTOR(6 downto 0);END xianshi;ARCHITECTURE xianshi_architecture OF xianshi ISBEGIN process(a) begin case a is when "0000" => y1<="1111110&qu

6、ot;y0<="1111110" when "0001" => y1<="1111110"y0<="0110000" when "0010" => y1<="1111110"y0<="1101101" when "0011" => y1<="1111110"y0<="1111001" when "0100" =>

7、 y1<="1111110"y0<="0110011" when "0101" => y1<="1111110"y0<="1011011" when "0110" => y1<="1111110"y0<="1011111" when "0111" => y1<="1111110"y0<="1110000" whe

8、n "1000" => y1<="1111110"y0<="1111111" when "1001" => y1<="1111110"y0<="1111011" when "1010" => y1<="0110000"y0<="1111110" when OTHERS => y1<="0110000"y0<="011

9、0000" end case; end process; END xianshi_architecture;甲乙方得分顯示模塊圖形輸入為：3、加減計數(shù)模塊通過的取值實現(xiàn)加或者減的計數(shù)。圖形：說明：ud=1時，計數(shù)器進(jìn)行減計數(shù)；ud=0時，計數(shù)器進(jìn)行加計數(shù)；s=0時，計數(shù)器正常工作；s=1時，計數(shù)器停止工作；reset=1時，計數(shù)器正常計數(shù)；reset=0時，計數(shù)器置數(shù)操作。VHDL語言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jishu ISPORT(ud : IN

10、 STD_LOGIC;s : IN STD_LOGIC;reset : IN STD_LOGIC;d3,d2,d1,d0 : IN std_logic;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jishu;ARCHITECTURE jishu_architecture OF jishu ISBEGIN process(ud,s,reset,clk) begin if(reset='0') then q(3)<=d3; q(2)<=d2; q(1)<=d1; q(0)<=d

11、0; else if(s='1') then q<=q; else if(clk'event and clk='1') then if(ud='1') then if(q="0000") then q<="1001" else q<=q-1; end if; else if(q="1001") then q<="0000" else q<=q+1; end if; end if; else q<=q; end if; end

12、 if; end if; end process;END jishu_architecture;4、譯碼模塊通過加減計數(shù)得到譯碼器輸出。加減計數(shù)、譯碼顯示真值表：時鐘加/減控制計數(shù)器輸出譯碼器輸出clkUd 0000000011111110 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 00 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 10 0 0 0 0 0 0 10 0 0 0 0 0 1 00 0 0 0 0 1 0 00 0 0 0 1 0 0 00 0 0 1 0 0 0 00

13、 0 1 0 0 0 0 00 1 0 0 0 0 0 01 0 0 0 0 0 0 00 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 1譯碼圖形：VHDL語言：LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY yima ISPORT(a : IN STD_LOGIC_VECTOR(3 downto 0);y : OUT STD

14、_LOGIC_VECTOR(9 downto 0);END yima;ARCHITECTURE yima_architecture OF yima ISBEGIN process(a) begin case a is when "0000" => y<="0000000001" when "0001" => y<="0000000010" when "0010" => y<="0000000100" when "0011"

15、; => y<="0000001000" when "0100" => y<="0000010000" when "0101" => y<="0000100000" when "0110" => y<="0001000000" when "0111" => y<="0010000000" when "1000" => y<=&

16、quot;0100000000" when others => y<="1000000000" end case; end process; END yima_architecture;5、控制模塊1、設(shè)置甲乙兩方擊球脈沖信號in1、in2，甲方擊球信號使得加減計數(shù)器加法計數(shù)，乙方擊球信號使得加減計數(shù)器減法計數(shù)，譯碼模塊輸出端Y1-Y8接LED模擬乒乓球的軌跡，Y0、Y9為球掉出桌外信號，控制模塊實現(xiàn)移位方向的控制。2、設(shè)置發(fā)球權(quán)擁有顯示信號S1、S2，控制模塊使每兩次交換發(fā)球權(quán)。3、設(shè)置撿球信號reset1，通過加減計數(shù)模塊的異步置數(shù)端實現(xiàn)撿球，當(dāng)甲

17、方擁有發(fā)球權(quán)時，撿球信號將球放到Y(jié)1；乙方擁有發(fā)球權(quán)時，撿球信號將球放到Y(jié)8。4、對甲、乙雙方的得分進(jìn)行檢測，只要有一方的得分達(dá)到11，則一局結(jié)束。5、設(shè)置裁判復(fù)位信號reset，在每局結(jié)束后將雙方得分清零。控制模塊與譯碼模塊和加減計數(shù)模塊的連接：部分控制模塊中VHDL語言及圖形：1、jishu2LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jishu2 ISPORT(clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(1 downto 0

18、);END jishu2;ARCHITECTURE jishu2_architecture OF jishu2 ISBEGIN process(clk) begin if(clk'event and clk='1') then if(q="11") then q<="00" else q<=q+1; end if; end if; end process;END jishu2_architecture;2、xuanzeLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.s

19、td_logic_unsigned.all;ENTITY xuanze ISPORT(a : IN STD_LOGIC;q1: in std_logic;q2: in std_logic;q : out STD_LOGIC);END xuanze;ARCHITECTURE xuanze_architecture OF xuanze ISBEGIN process(a) begin if(a='1') then q<=q2; else q<=q1; end if; end process;END xuanze_architecture;3、dchufaqiLIBRAR

20、Y ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY dchufaqi ISPORT(d : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC);END dchufaqi;ARCHITECTURE dchufaqi_architecture OF dchufaqi ISBEGIN process(clk) begin if(clk'event and clk='0') then q<=d; else q<=q;

21、 end if; end process;END dchufaqi_architecture;6、核心問題1、由于實驗箱上的頻率為50MHz，譯碼器輸出變化太快，顯示在實驗箱上的8個LED閃亮變化太快，以致無法識別。因此需要降低頻率后在接到加減計數(shù)模塊的clk端。圖形：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yanshi is port (clk: in std_logic;y: buffer std_logic_vector(24 downto 0) );end yansh

22、i;architecture behave of yanshi isVHDL語言： begin process(clk) begin if(clk'event and clk='1') then if(y="1000000000000000000000000" or y="1111111111111111111111111") then y<="0000000000000000000000000" else y<=y+1; end if; end if; end process;end behave

23、;2、在數(shù)碼管上動態(tài)顯示甲乙雙方的得分。動態(tài)顯示模塊：1、dongtaixianshi1的VHDL語言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dongtaixianshi1 is port ( clk: IN STD_LOGIC;y: buffer std_logic_vector(1 downto 0) );end dongtaixianshi1; architecture behave of dongtaixianshi1 is begin process(clk) b

24、egin if(clk'event and clk='1') then if(y="11") then y<="00" else y<=y+1; end if; end if; end process;end behave;2、dongtaixianshi2的VHDL語言：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dongtaixianshi2 is port (a: in std_logic_vect

25、or(1 downto 0);yjia1,yjia0,yyi1,yyi0: in STD_LOGIC_VECTOR(6 downto 0);y: out std_logic_vector(6 downto 0);pianxuan: out std_logic_vector(3 downto 0) );end dongtaixianshi2; architecture behave of dongtaixianshi2 is begin process(a) begin case a is when "00" => y<=yjia1;pianxuan<=&q

26、uot;0111" when "01" => y<=yjia0;pianxuan<="1011" when "10" => y<=yyi1;pianxuan<="1101" when OTHERS => y<=yyi0;pianxuan<="1110" end case; end process;end behave;三、結(jié)果分析注：本實驗采取實際測試的方法。采用Altera新一代的MAX器件EPM570T100C5。 程序下載方法

27、采用ByteBlaster。1、分配引腳：符號分配引腳名稱備注in1pin_27K201選手甲，按下即為擊球。in2pin_30K204選手乙，按下即為擊球。resetpin_33S205裁判，撥盤開關(guān)撥到左邊即為將雙方得分清零。clkpin_62CLK時鐘信號。reset1pin_34S206裁判，撥盤開關(guān)先撥到左邊后撥到右邊即為分配發(fā)球權(quán)。y18pin_50D208Y18.1連到實驗箱的8個LED。當(dāng)Y18亮?xí)r，要求乙迅速擊球，當(dāng)Y11亮，要求甲迅速擊球。若擊中，點(diǎn)亮的LED會依次從左到右或從右到左；若未擊中，球跳出桌外，對方得一分。y17pin_49D207y16pin_48D206y1

28、5pin_47D205y14pin_42D204y13pin_41D203y12pin_40D202y11pin_38D201y6pin_81a顯示計分y5pin_82by4pin_83cy3pin_84dy2pin_85ey1pin_86fy0pin_87gpianxuan3pin_91S0pianxuan2pin_92S1pianxuan1pin_99S6pianxuan0pin_100S72、分析：（1）經(jīng)測試，完全符合要求。（2）上述設(shè)計的乒乓球比賽游戲機(jī)用到了自下而上的層次化設(shè)計方法，用到了VHDL語言設(shè)計輸入方法和原理圖設(shè)計輸入方法。（3）由調(diào)節(jié)晶振產(chǎn)生的時鐘脈沖信號的頻率，可以調(diào)

29、節(jié)球的運(yùn)動速度。四、附件1、完整電路圖2、各個自制元件的VHDL程序（1）dchufaqiLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY dchufaqi ISPORT(d : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC);END dchufaqi;ARCHITECTURE dchufaqi_architecture OF dchufaqi ISBEGIN process(clk) begin if(clk'eve

30、nt and clk='0') then q<=d; else q<=q; end if; end process;END dchufaqi_architecture;（2）dongtaixianshi1library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dongtaixianshi1 is port ( clk: IN STD_LOGIC;y: buffer std_logic_vector(1 downto 0) );end dongtaixianshi1

31、; architecture behave of dongtaixianshi1 is begin process(clk) begin if(clk'event and clk='1') then if(y="11") then y<="00" else y<=y+1; end if; end if; end process;end behave;（3）dongtaixianshi2library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned

32、.all;entity dongtaixianshi2 is port (a: in std_logic_vector(1 downto 0);yjia1,yjia0,yyi1,yyi0: in STD_LOGIC_VECTOR(6 downto 0);y: out std_logic_vector(6 downto 0);pianxuan: out std_logic_vector(3 downto 0) );end dongtaixianshi2; architecture behave of dongtaixianshi2 is begin process(a) begin case a

33、 is when "00" => y<=yjia1;pianxuan<="0111" when "01" => y<=yjia0;pianxuan<="1011" when "10" => y<=yyi1;pianxuan<="1101" when OTHERS => y<=yyi0;pianxuan<="1110" end case; end process;end behave;（

34、4）fenpinlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin is port ( clk: in std_logic; clk1: out std_logic );end fenpin; architecture behave of fenpin issignal cnt1: std_logic_vector(25 downto 0);begin process(clk) begin if(clk'event and clk='1') then

35、 cnt1<=cnt1+1; end if; end process; clk1<=cnt1(15);end behave;（5）jifenLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jifen ISPORT(reset : IN STD_LOGIC;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jifen;ARCHITECTURE jifen_architecture OF jifen

36、ISBEGIN process(clk,reset) begin if(reset='0') then q<="0000" elsif(clk'event and clk='1') then if(q="1011") then q<="1011" else q<=q+1; end if; end if; end process;END jifen_architecture;（6）jishuLIBRARY ieee;USE ieee.std_logic_1164.all;use

37、ieee.std_logic_unsigned.all;ENTITY jishu ISPORT(ud : IN STD_LOGIC;s : IN STD_LOGIC;reset : IN STD_LOGIC;d3,d2,d1,d0 : IN std_logic;clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(3 downto 0);END jishu;ARCHITECTURE jishu_architecture OF jishu ISBEGIN process(ud,s,reset,clk) begin if(reset='0')

38、 then q(3)<=d3; q(2)<=d2; q(1)<=d1; q(0)<=d0; else if(s='1') then q<=q; else if(clk'event and clk='1') then if(ud='1') then if(q="0000") then q<="1001" else q<=q-1; end if; else if(q="1001") then q<="0000" el

39、se q<=q+1; end if; end if; else q<=q; end if; end if; end if; end process;END jishu_architecture;（7）jishu2LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jishu2 ISPORT(clk : IN STD_LOGIC;q : buffer STD_LOGIC_VECTOR(1 downto 0);END jishu2;ARCHITECTURE jishu2_arch

40、itecture OF jishu2 ISBEGIN process(clk) begin if(clk'event and clk='1') then if(q="11") then q<="00" else q<=q+1; end if; end if; end process;END jishu2_architecture;（8）xianshiLIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY xiansh

41、i ISPORT(a : IN STD_LOGIC_VECTOR(3 downto 0);y1 : OUT STD_LOGIC_VECTOR(6 downto 0);y0 : OUT STD_LOGIC_VECTOR(6 downto 0);END xianshi;ARCHITECTURE xianshi_architecture OF xianshi ISBEGIN process(a) begin case a is when "0000" => y1<="1111110"y0<="1111110" when &

42、quot;0001" => y1<="1111110"y0<="0110000" when "0010" => y1<="1111110"y0<="1101101" when "0011" => y1<="1111110"y0<="1111001" when "0100" => y1<="1111110"y0<=&q

43、uot;0110011" when "0101" => y1<="1111110"y0<="1011011" when "0110" => y1<="1111110"y0<="1011111" when "0111" => y1<="1111110"y0<="1110000" when "1000" => y1<="1111110"y0<="1111111" when